MIPS: Add MIN/MAX.fmt instructions support for MIPS R6
This patch adds the smin/smax RTL mode for the min/max.fmt instructions. Also, since the min/max.fmt instrucions applies to the IEEE 754-2008 "minNum" and "maxNum" operations, this patch also provides the new "fmin<mode>3" and "fmax<mode>3" modes. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_minmax): New define_insn_reservation. * config/mips/mips.h (ISA_HAS_FMIN_FMAX): Define new macro. * config/mips/mips.md (UNSPEC_FMIN): New unspec. (UNSPEC_FMAX): Same as above. (type): Add fminmax. (smin<mode>3): Generates MIN.fmt instructions. (smax<mode>3): Generates MAX.fmt instructions. (fmin<mode>3): Generates MIN.fmt instructions. (fmax<mode>3): Generates MAX.fmt instructions. * config/mips/p6600.md (p6600_fpu_fabs): Include fminmax type. gcc/testsuite/ChangeLog: * gcc.target/mips/mips-minmax1.c: New test for MIPS R6. * gcc.target/mips/mips-minmax2.c: Same as above.
This commit is contained in:
Jie Mei
YunQiang Su
parent
deb69bfbb0
commit
11c13111ac
6 changed files with 134 additions and 4 deletions
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@ -219,6 +219,12 @@
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(eq_attr "type" "fabs,fneg,fmove"))
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"i6400_fpu_short, i6400_fpu_apu")
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;; min, max
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(define_insn_reservation "i6400_fpu_minmax" 2
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "fminmax"))
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"i6400_fpu_short+i6400_fpu_logic")
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;; fadd, fsub, fcvt
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(define_insn_reservation "i6400_fpu_fadd" 4
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(and (eq_attr "cpu" "i6400")
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@ -1262,6 +1262,8 @@ struct mips_cpu_info {
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#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \
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|| ISA_HAS_MIPS16E2)
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#define ISA_HAS_FMIN_FMAX (mips_isa_rev >= 6)
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/* ISA has data indexed prefetch instructions. This controls use of
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'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
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(prefx is a cop1x instruction, so can only be used if FP is
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@ -97,6 +97,10 @@
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UNSPEC_GET_FCSR
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UNSPEC_SET_FCSR
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;; Floating-point unspecs.
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UNSPEC_FMIN
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UNSPEC_FMAX
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;; HI/LO moves.
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UNSPEC_MFHI
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UNSPEC_MTHI
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@ -370,6 +374,7 @@
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;; frsqrt floating point reciprocal square root
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;; frsqrt1 floating point reciprocal square root step1
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;; frsqrt2 floating point reciprocal square root step2
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;; fminmax floating point min/max
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;; dspmac DSP MAC instructions not saturating the accumulator
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;; dspmacsat DSP MAC instructions that saturate the accumulator
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;; accext DSP accumulator extract instructions
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@ -387,8 +392,8 @@
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prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
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shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
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fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
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frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
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multi,atomic,syncloop,nop,ghost,multimem,
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frsqrt,frsqrt1,frsqrt2,fminmax,dspmac,dspmacsat,accext,accmod,dspalu,
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dspalusat,multi,atomic,syncloop,nop,ghost,multimem,
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simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd,
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simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp,
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simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill,
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@ -7971,6 +7976,47 @@
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[(set_attr "move_type" "load")
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(set_attr "insn_count" "2")])
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;;
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;; Float point MIN/MAX
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;;
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(define_insn "smin<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(smin:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
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(match_operand:SCALARF 2 "register_operand" "f")))]
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"ISA_HAS_FMIN_FMAX"
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"min.<fmt>\t%0,%1,%2"
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[(set_attr "type" "fminmax")
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(set_attr "mode" "<UNITMODE>")])
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(define_insn "smax<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(smax:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
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(match_operand:SCALARF 2 "register_operand" "f")))]
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"ISA_HAS_FMIN_FMAX"
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"max.<fmt>\t%0,%1,%2"
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[(set_attr "type" "fminmax")
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(set_attr "mode" "<UNITMODE>")])
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(define_insn "fmin<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(unspec:SCALARF [(use (match_operand:SCALARF 1 "register_operand" "f"))
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(use (match_operand:SCALARF 2 "register_operand" "f"))]
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UNSPEC_FMIN))]
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"ISA_HAS_FMIN_FMAX"
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"min.<fmt>\t%0,%1,%2"
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[(set_attr "type" "fminmax")
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(set_attr "mode" "<UNITMODE>")])
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(define_insn "fmax<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(unspec:SCALARF [(use (match_operand:SCALARF 1 "register_operand" "f"))
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(use (match_operand:SCALARF 2 "register_operand" "f"))]
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UNSPEC_FMAX))]
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"ISA_HAS_FMIN_FMAX"
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"max.<fmt>\t%0,%1,%2"
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[(set_attr "type" "fminmax")
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(set_attr "mode" "<UNITMODE>")])
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;; 2 HI loads are joined.
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(define_peephole2
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@ -167,10 +167,10 @@
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(eq_attr "type" "fadd"))
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"p6600_fpu_long, p6600_fpu_apu")
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;; fabs, fneg, fcmp
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;; fabs, fneg, fcmp, fminmax
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(define_insn_reservation "p6600_fpu_fabs" 2
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(and (eq_attr "cpu" "p6600")
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(ior (eq_attr "type" "fabs,fneg,fcmp,fmove")
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(ior (eq_attr "type" "fabs,fneg,fcmp,fmove,fminmax")
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(and (eq_attr "type" "condmove")
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(eq_attr "mode" "SF,DF"))))
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"p6600_fpu_short, p6600_fpu_apu")
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40
gcc/testsuite/gcc.target/mips/mips-minmax1.c
Normal file
40
gcc/testsuite/gcc.target/mips/mips-minmax1.c
Normal file
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@ -0,0 +1,40 @@
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/* { dg-do compile } */
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/* { dg-options "-mhard-float -fno-finite-math-only -march=mips32r6" } */
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/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
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/* Test MIN.D. */
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/* { dg-final { scan-assembler "\tmin\\.d\t" } } */
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double
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test01 (double x, double y)
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{
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return __builtin_fmin (x, y);
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}
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/* Test MIN.S. */
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/* { dg-final { scan-assembler "\tmin\\.s\t" } } */
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float
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test02 (float x, float y)
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{
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return __builtin_fminf (x, y);
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}
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/* Test MAX.D. */
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/* { dg-final { scan-assembler "\tmax\\.d\t" } } */
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double
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test03 (double x, double y)
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{
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return __builtin_fmax (x, y);
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}
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/* Test MAX.S. */
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/* { dg-final { scan-assembler "\tmax\\.s\t" } } */
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float
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test04 (float x, float y)
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{
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return __builtin_fmaxf (x, y);
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}
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36
gcc/testsuite/gcc.target/mips/mips-minmax2.c
Normal file
36
gcc/testsuite/gcc.target/mips/mips-minmax2.c
Normal file
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@ -0,0 +1,36 @@
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/* { dg-do compile } */
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/* { dg-options "-mhard-float -march=mips32r6" } */
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/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
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extern double fmin (double, double);
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extern double fmax (double, double);
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extern float fminf (float, float);
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extern float fmaxf (float, float);
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/* Test MIN.D. */
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/* { dg-final { scan-assembler "\tmin\\.d\t" } } */
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double test01 (double x, double y) {
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return fmin (x, y);
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}
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/* Test MIN.S. */
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/* { dg-final { scan-assembler "\tmin\\.s\t" } } */
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float test02 (float x, float y) {
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return fminf (x, y);
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}
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/* Test MAX.D. */
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/* { dg-final { scan-assembler "\tmax\\.d\t" } } */
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double test03 (double x, double y) {
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return fmax (x, y);
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}
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/* Test MAX.S. */
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/* { dg-final { scan-assembler "\tmax\\.s\t" } } */
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float test04 (float x, float y) {
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return fmaxf (x, y);
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}
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