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darwin-c.c, [...]: Fix comment typos.

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* config/darwin-c.c, config/arc/arc.c, config/arc/arc.md,
	config/arm/README-interworking, config/arm/arm-cores.def,
	config/arm/arm.c, config/arm/arm.h, config/arm/pe.c,
	config/arm/vfp.md, config/c4x/c4x.c, config/c4x/c4x.h,
	config/cris/cris.c, config/cris/cris.h, config/fr30/fr30.c,
	config/fr30/fr30.h, config/fr30/fr30.md, config/frv/frv.c,
	config/frv/frv.md, config/i386/winnt.c,
	config/ia64/unwind-ia64.c, config/iq2000/iq2000.c,
	config/iq2000/iq2000.h, config/m68hc11/m68hc11.c,
	config/m68hc11/m68hc11.md, config/m68k/m68k.c,
	config/mcore/mcore.c, config/mips/mips.h,
	config/mn10300/mn10300.md, config/pa/pa.c,
	config/pa/pa64-regs.h, config/pdp11/pdp11.c,
	config/rs6000/rs6000.c, config/sh/symbian.c,
	config/sparc/sparc.h: Fix comment typos.  Follow spelling
	conventions.

From-SVN: r87706
This commit is contained in:
Kazu Hirata 2004-09-18 19:19:40 +00:00 • committed by Kazu Hirata
parent ad97f4bed6
commit 112cdef5e6
35 changed files with 84 additions and 65 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
gcc/ChangeLog
View file

@ -1,3 +1,22 @@
2004-09-18 Kazu Hirata <kazu@cs.umass.edu>
* config/darwin-c.c, config/arc/arc.c, config/arc/arc.md,
config/arm/README-interworking, config/arm/arm-cores.def,
config/arm/arm.c, config/arm/arm.h, config/arm/pe.c,
config/arm/vfp.md, config/c4x/c4x.c, config/c4x/c4x.h,
config/cris/cris.c, config/cris/cris.h, config/fr30/fr30.c,
config/fr30/fr30.h, config/fr30/fr30.md, config/frv/frv.c,
config/frv/frv.md, config/i386/winnt.c,
config/ia64/unwind-ia64.c, config/iq2000/iq2000.c,
config/iq2000/iq2000.h, config/m68hc11/m68hc11.c,
config/m68hc11/m68hc11.md, config/m68k/m68k.c,
config/mcore/mcore.c, config/mips/mips.h,
config/mn10300/mn10300.md, config/pa/pa.c,
config/pa/pa64-regs.h, config/pdp11/pdp11.c,
config/rs6000/rs6000.c, config/sh/symbian.c,
config/sparc/sparc.h: Fix comment typos. Follow spelling
conventions.
2004-09-18 Joseph S. Myers <jsm@polyomino.org.uk>
PR c/17424

2
gcc/config/arc/arc.c
View file

@ -1971,7 +1971,7 @@ arc_final_prescan_insn (rtx insn,
/* BODY will hold the body of INSN. */
register rtx body = PATTERN (insn);
/* This will be 1 if trying to repeat the trick (ie: do the `else' part of
/* This will be 1 if trying to repeat the trick (i.e.: do the `else' part of
an if/then/else), and things need to be reversed. */
int reverse = 0;

2
gcc/config/arc/arc.md
View file

@ -69,7 +69,7 @@
;; conditionalizing instructions. It saves having to scan the rtl to see if
;; it uses or alters the condition codes.
;; USE: This insn uses the condition codes (eg: a conditional branch).
;; USE: This insn uses the condition codes (e.g.: a conditional branch).
;; CANUSE: This insn can use the condition codes (for conditional execution).
;; SET: All condition codes are set by this insn.
;; SET_ZN: the Z and N flags are set by this insn.

2
gcc/config/arm/README-interworking
View file

@ -78,7 +78,7 @@ then the following rules must be obeyed:
* All externally visible functions which should be entered in
Thumb mode must have the .thumb_func pseudo op specified just
before their entry point. eg:
before their entry point. e.g.:
.code 16
.global function

2
gcc/config/arm/arm-cores.def
View file

@ -25,7 +25,7 @@
The CORE_NAME is the name of the core, represented as a string constant.
The CORE_IDENT is the name of the core, represented as an identifier.
ARCH is the architecture revision implemeted by the chip.
ARCH is the architecture revision implemented by the chip.
FLAGS are the bitwise-or of the traits that apply to that core.
This need not include flags implied by the architecture.
COSTS is the name of the rtx_costs routine to use.

20
gcc/config/arm/arm.c
View file

@ -2108,7 +2108,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
Therefore, we calculate how many insns would be required to emit
the constant starting from `best_start', and also starting from
zero (ie with bit 31 first to be output). If `best_start' doesn't
zero (i.e. with bit 31 first to be output). If `best_start' doesn't
yield a shorter sequence, we may as well use zero. */
if (best_start != 0
&& ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
@ -3133,7 +3133,7 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
{
rtx addend = XEXP (XEXP (x, 1), 1);
/* Don't allow ldrd post increment by register becuase it's hard
/* Don't allow ldrd post increment by register because it's hard
to fixup invalid register choices. */
if (use_ldrd
&& GET_CODE (x) == POST_MODIFY
@ -5051,7 +5051,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
abort ();
/* Loop over the operands and check that the memory references are
suitable (ie immediate offsets from the same base register). At
suitable (i.e. immediate offsets from the same base register). At
the same time, extract the target register, and the memory
offsets. */
for (i = 0; i < nops; i++)
@ -5280,7 +5280,7 @@ store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
abort ();
/* Loop over the operands and check that the memory references are
suitable (ie immediate offsets from the same base register). At
suitable (i.e. immediate offsets from the same base register). At
the same time, extract the target register, and the memory
offsets. */
for (i = 0; i < nops; i++)
@ -8844,7 +8844,7 @@ output_return_instruction (rtx operand, int really_return, int reverse)
const char * return_reg;
/* If we do not have any special requirements for function exit
(eg interworking, or ISR) then we can load the return address
(e.g. interworking, or ISR) then we can load the return address
directly into the PC. Otherwise we must load it into LR. */
if (really_return
&& ! TARGET_INTERWORK)
@ -9408,7 +9408,7 @@ arm_output_epilogue (rtx sibling)
{
if (saved_regs_mask & (1 << SP_REGNUM))
/* Note - write back to the stack register is not enabled
(ie "ldmfd sp!..."). We know that the stack pointer is
(i.e. "ldmfd sp!..."). We know that the stack pointer is
in the list of registers and if we add writeback the
instruction becomes UNPREDICTABLE. */
print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
@ -10422,7 +10422,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return;
case 'D':
/* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
/* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
want to do that. */
if (x == const_true_rtx)
abort ();
@ -11002,7 +11002,7 @@ arm_final_prescan_insn (rtx insn)
else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
fail = TRUE;
}
/* Fail if a conditional return is undesirable (eg on a
/* Fail if a conditional return is undesirable (e.g. on a
StrongARM), but still allow this if optimizing for size. */
else if (GET_CODE (scanbody) == RETURN
&& !use_return_insn (TRUE, NULL)
@ -11026,7 +11026,7 @@ arm_final_prescan_insn (rtx insn)
}
}
else
fail = TRUE; /* Unrecognized jump (eg epilogue). */
fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
break;
@ -12650,7 +12650,7 @@ thumb_unexpanded_epilogue (void)
size = GET_MODE_SIZE (mode);
/* The prolog may have pushed some high registers to use as
work registers. eg the testsuite file:
work registers. e.g. the testsuite file:
gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
compiles to produce:
push {r4, r5, r6, r7, lr}

2
gcc/config/arm/arm.h
View file

@ -1595,7 +1595,7 @@ enum reg_class
#define CALL_SHORT 0x00000002 /* Never call indirect. */
/* These bits describe the different types of function supported
by the ARM backend. They are exclusive. ie a function cannot be both a
by the ARM backend. They are exclusive. i.e. a function cannot be both a
normal function and an interworked function, for example. Knowing the
type of a function is important for determining its prologue and
epilogue sequences.

2
gcc/config/arm/pe.c
View file

@ -96,7 +96,7 @@ arm_dllimport_name_p (symbol)
}
/* Mark a DECL as being dllexport'd.
Note that we override the previous setting (eg: dllimport). */
Note that we override the previous setting (e.g.: dllimport). */
void
arm_mark_dllexport (decl)

2
gcc/config/arm/vfp.md
View file

@ -56,7 +56,7 @@
(define_cpu_unit "vfp_ls" "vfp11")
;; The VFP "type" attributes differ from those used in the FPA model.
;; ffarith Fast floating point insns, eg. abs, neg, cpy, cmp.
;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
;; farith Most arithmetic insns.
;; fmul Double precision multiply.
;; fdivs Single precision sqrt or division.

4
gcc/config/c4x/c4x.c
View file

@ -3342,7 +3342,7 @@ tsrc_operand (rtx op, enum machine_mode mode)
}
/* Check src operand of two operand non immedidate instructions. */
/* Check src operand of two operand non immediate instructions. */
int
nonimmediate_src_operand (rtx op, enum machine_mode mode)
@ -3354,7 +3354,7 @@ nonimmediate_src_operand (rtx op, enum machine_mode mode)
}
/* Check logical src operand of two operand non immedidate instructions. */
/* Check logical src operand of two operand non immediate instructions. */
int
nonimmediate_lsrc_operand (rtx op, enum machine_mode mode)

2
gcc/config/c4x/c4x.h
View file

@ -1372,7 +1372,7 @@ CUMULATIVE_ARGS;
#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
/* Descripting Relative Cost of Operations. */
/* Describing Relative Cost of Operations. */
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
if (REG_P (OP1) && ! REG_P (OP0)) \

2
gcc/config/cris/cris.c
View file

@ -3099,7 +3099,7 @@ restart:
break;
case PLUS:
/* Some assemblers need integer constants to appear last (eg masm). */
/* Some assemblers need integer constants to appear last (e.g. masm). */
if (GET_CODE (XEXP (x, 0)) == CONST_INT)
{
cris_output_addr_const (file, XEXP (x, 1));

2
gcc/config/cris/cris.h
View file

@ -336,7 +336,7 @@ extern int target_flags;
/* Whether or not to work around multiplication instruction hardware bug
when generating code for models where it may be present. From the
trouble report for Etrax 100 LX: "A multiply operation may cause
incorrect cache behaviour under some specific circumstances. The
incorrect cache behavior under some specific circumstances. The
problem can occur if the instruction following the multiply instruction
causes a cache miss, and multiply operand 1 (source operand) bits
[31:27] matches the logical mapping of the mode register address

2
gcc/config/darwin-c.c
View file

@ -442,7 +442,7 @@ darwin_register_objc_includes (const char *sysroot, const char *iprefix,
{
char *str;
/* See if our directory starts with the standard prefix.
"Translate" them, ie. replace /usr/local/lib/gcc... with
"Translate" them, i.e. replace /usr/local/lib/gcc... with
IPREFIX and search them first. */
if (iprefix && (len = cpp_GCC_INCLUDE_DIR_len) != 0 && !sysroot
&& !strncmp (fname, cpp_GCC_INCLUDE_DIR, len))

2
gcc/config/fr30/fr30.c
View file

@ -709,7 +709,7 @@ int
fr30_function_arg_partial_nregs (CUMULATIVE_ARGS cum, enum machine_mode mode,
tree type, int named)
{
/* Unnamed arguments, ie those that are prototyped as ...
/* Unnamed arguments, i.e. those that are prototyped as ...
are always passed on the stack.
Also check here to see if all the argument registers are full. */
if (named == 0 || cum >= FR30_NUM_ARG_REGS)

2
gcc/config/fr30/fr30.h
View file

@ -293,7 +293,7 @@ enum reg_class
MULTIPLY_64_REG, /* the MDH,MDL register pair as used by MUL and MULU */
LOW_REGS, /* registers 0 through 7 */
HIGH_REGS, /* registers 8 through 15 */
REAL_REGS, /* ie all the general hardware registers on the FR30 */
REAL_REGS, /* i.e. all the general hardware registers on the FR30 */
ALL_REGS,
LIM_REG_CLASSES
};

6
gcc/config/fr30/fr30.md
View file

@ -370,7 +370,7 @@
;; Note - the FR30 does not have an 8 byte load/store instruction
;; but we have to support this pattern because some other patterns
;; (eg muldisi2) can produce a DImode result.
;; (e.g. muldisi2) can produce a DImode result.
;; (This code is stolen from the M32R port.)
(define_expand "movdi"
@ -637,7 +637,7 @@
)
;; We need some trickery to be able to handle the addition of
;; large (ie outside +/- 16) constants. We need to be able to
;; large (i.e. outside +/- 16) constants. We need to be able to
;; handle this because reload assumes that it can generate add
;; instructions with arbitrary sized constants.
(define_expand "addsi3"
@ -1153,7 +1153,7 @@
;; -256 <= pc < 256
;; or
;; -256 + 256 <= pc + 256 < 256 + 256
;; ie
;; i.e.
;; 0 <= pc + 256 < 512
;;
;; if we consider the displacement as an unsigned value, then negative

2
gcc/config/frv/frv.c
View file

@ -9551,7 +9551,7 @@ frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
rtx reg;
int i;
/* ACCs and ACCGs are implicity global registers if media instrinsics
/* ACCs and ACCGs are implicity global registers if media intrinsics
are being used. We set up this lazily to avoid creating lots of
unnecessary call_insn rtl in non-media code. */
for (i = 0; i <= ACC_MASK; i++)

2
gcc/config/frv/frv.md
View file

@ -1445,7 +1445,7 @@
;; If you need to construct a sequence of assembler instructions in order
;; to implement a pattern be sure to escape any backslashes and double quotes
;; that you use, eg:
;; that you use, e.g.:
;;
;; (define_insn "an example"
;; [(some rtl)]

2
gcc/config/i386/winnt.c
View file

@ -231,7 +231,7 @@ i386_pe_dllimport_name_p (const char *symbol)
}
/* Mark a DECL as being dllexport'd.
Note that we override the previous setting (eg: dllimport). */
Note that we override the previous setting (e.g.: dllimport). */
static void
i386_pe_mark_dllexport (tree decl)

2
gcc/config/ia64/unwind-ia64.c
View file

@ -2111,7 +2111,7 @@ uw_init_context_1 (struct _Unwind_Context *context, void *bsp)
uw_update_context (context, &fs);
}
/* Install (ie longjmp to) the contents of TARGET. */
/* Install (i.e. longjmp to) the contents of TARGET. */
static void __attribute__((noreturn))
uw_install_context (struct _Unwind_Context *current __attribute__((unused)),

4
gcc/config/iq2000/iq2000.c
View file

@ -143,7 +143,7 @@ static int dslots_jump_total;
/* # of nops needed by previous insn. */
static int dslots_number_nops;
/* Number of 1/2/3 word references to data items (ie, not jal's). */
/* Number of 1/2/3 word references to data items (i.e., not jal's). */
static int num_refs[3];
/* Registers to check for load delay. */
@ -293,7 +293,7 @@ reg_or_0_operand (rtx op, enum machine_mode mode)
}
/* Return 1 if OP is a memory operand that fits in a single instruction
(ie, register + small offset). */
(i.e., register + small offset). */
int
simple_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)

6
gcc/config/iq2000/iq2000.h
View file

@ -307,16 +307,16 @@ enum reg_class
`I' is used for the range of constants an arithmetic insn can
actually contain (16 bits signed integers).
`J' is used for the range which is just zero (ie, $r0).
`J' is used for the range which is just zero (i.e., $r0).
`K' is used for the range of constants a logical insn can actually
contain (16 bit zero-extended integers).
`L' is used for the range of constants that be loaded with lui
(ie, the bottom 16 bits are zero).
(i.e., the bottom 16 bits are zero).
`M' is used for the range of constants that take two words to load
(ie, not matched by `I', `K', and `L').
(i.e., not matched by `I', `K', and `L').
`N' is used for constants 0xffffnnnn or 0xnnnnffff

2
gcc/config/m68hc11/m68hc11.c
View file

@ -850,7 +850,7 @@ m68hc11_reload_operands (rtx operands[])
/* If the offset is out of range, we have to compute the address
with a separate add instruction. We try to do with with an 8-bit
add on the A register. This is possible only if the lowest part
of the offset (ie, big_offset % 256) is a valid constant offset
of the offset (i.e., big_offset % 256) is a valid constant offset
with respect to the mode. If it's not, we have to generate a
16-bit add on the D register. From:

6
gcc/config/m68hc11/m68hc11.md
View file

@ -67,7 +67,7 @@
;; Other constraints:
;;
;; Q an operand which is in memory but whose address is constant
;; (ie, a (MEM (SYMBOL_REF x))). This constraint is used by
;; (i.e., a (MEM (SYMBOL_REF x))). This constraint is used by
;; bset/bclr instructions together with linker relaxation. The
;; operand can be translated to a page0 addressing mode if the
;; symbol address is in page0 (0..255).
@ -157,7 +157,7 @@
;; an auto-inc mode. If we do this, the reload can emit move insns
;; after the test or compare. Such move will set the flags and therefore
;; break the comparison. This can happen if the auto-inc register
;; does not happen to be a hard register (ie, reloading occurs).
;; does not happen to be a hard register (i.e., reloading occurs).
;; An offsetable memory operand should be ok. The 'tst_operand' and
;; 'cmp_operand' predicates take care of this rule.
;;
@ -242,7 +242,7 @@
;;
;; tstqi_z_used, cmpqi_z_used and cmphi_z_used are patterns generated
;; during the Z register replacement. They are used when an operand
;; uses the Z register as an index register (ie, (MEM:QI (REG:HI Z))).
;; uses the Z register as an index register (i.e., (MEM:QI (REG:HI Z))).
;; In that case, we have to preserve the values of the replacement
;; register (as well as the CC0 since the insns are compare insns).
;; To do this, the replacement register is pushed on the stack and

4
gcc/config/m68k/m68k.c
View file

@ -2713,8 +2713,8 @@ print_operand (FILE *file, rtx op, int letter)
This routine is responsible for distinguishing between -fpic and -fPIC
style relocations in an address. When generating -fpic code the
offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
-fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
-fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
#if MOTOROLA
# define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\

4
gcc/config/mcore/mcore.c
View file

@ -321,7 +321,7 @@ mcore_print_operand_address (FILE * stream, rtx x)
/* Print operand x (an rtx) in assembler syntax to file stream
according to modifier code.
'R' print the next register or memory location along, ie the lsw in
'R' print the next register or memory location along, i.e. the lsw in
a double word value
'O' print a constant without the #
'M' print a constant as its negative
@ -2782,7 +2782,7 @@ conditionalize_block (rtx first)
if (code != BARRIER && code != NOTE && !is_cond_candidate (insn))
return NEXT_INSN (insn);
/* Remember the last real insn before the label (ie end of block 2). */
/* Remember the last real insn before the label (i.e. end of block 2). */
if (code == JUMP_INSN || code == INSN)
{
blk_size ++;

12
gcc/config/mips/mips.h
View file

@ -835,12 +835,12 @@ extern const struct mips_cpu_info *mips_tune_info;
ABI for which this is true. */
#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
|| ISA_MIPS64)
/* ISA has branch likely instructions (eg. mips2). */
/* ISA has branch likely instructions (e.g. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
@ -1922,16 +1922,16 @@ extern enum reg_class mips_char_to_class[256];
`I' is used for the range of constants an arithmetic insn can
actually contain (16 bits signed integers).
`J' is used for the range which is just zero (ie, $r0).
`J' is used for the range which is just zero (i.e., $r0).
`K' is used for the range of constants a logical insn can actually
contain (16 bit zero-extended integers).
`L' is used for the range of constants that be loaded with lui
(ie, the bottom 16 bits are zero).
(i.e., the bottom 16 bits are zero).
`M' is used for the range of constants that take two words to load
(ie, not matched by `I', `K', and `L').
(i.e., not matched by `I', `K', and `L').
`N' is used for negative 16 bit constants other than -65536.
@ -2824,7 +2824,7 @@ while (0)
#define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
/* This says how to define a local common symbol (ie, not visible to
/* This says how to define a local common symbol (i.e., not visible to
linker). */
#ifndef ASM_OUTPUT_ALIGNED_LOCAL

2
gcc/config/mn10300/mn10300.md
View file

@ -1547,7 +1547,7 @@
len--;
}
/* If the source operand is not a reg (ie it is memory), then extract the
/* If the source operand is not a reg (i.e. it is memory), then extract the
bits from mask that we actually want to test. Note that the mask will
never cross a byte boundary. */
if (!REG_P (operands[0]))

14
gcc/config/pa/pa.c
View file

@ -3459,7 +3459,7 @@ remove_useless_addtr_insns (int check_notes)
{
rtx pattern = PATTERN (next);
/* If it a reversed fp conditional branch (eg uses add,tr)
/* If it a reversed fp conditional branch (e.g. uses add,tr)
and CCFP dies, then reverse our conditional and the branch
to avoid the add,tr. */
if (GET_CODE (pattern) == SET
@ -6191,7 +6191,7 @@ output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
int useskip = 0;
rtx xoperands[5];
/* A conditional branch to the following instruction (eg the delay slot)
/* A conditional branch to the following instruction (e.g. the delay slot)
is asking for a disaster. This can happen when not optimizing and
when jump optimization fails.
@ -6500,7 +6500,7 @@ output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
static char buf[100];
int useskip = 0;
/* A conditional branch to the following instruction (eg the delay slot) is
/* A conditional branch to the following instruction (e.g. the delay slot) is
asking for a disaster. I do not think this can happen as this pattern
is only used when optimizing; jump optimization should eliminate the
jump. But be prepared just in case. */
@ -6645,7 +6645,7 @@ output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
static char buf[100];
int useskip = 0;
/* A conditional branch to the following instruction (eg the delay slot) is
/* A conditional branch to the following instruction (e.g. the delay slot) is
asking for a disaster. I do not think this can happen as this pattern
is only used when optimizing; jump optimization should eliminate the
jump. But be prepared just in case. */
@ -6785,7 +6785,7 @@ const char *
output_dbra (rtx *operands, rtx insn, int which_alternative)
{
/* A conditional branch to the following instruction (eg the delay slot) is
/* A conditional branch to the following instruction (e.g. the delay slot) is
asking for a disaster. Be prepared! */
if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
@ -6889,7 +6889,7 @@ output_movb (rtx *operands, rtx insn, int which_alternative,
int reverse_comparison)
{
/* A conditional branch to the following instruction (eg the delay slot) is
/* A conditional branch to the following instruction (e.g. the delay slot) is
asking for a disaster. Be prepared! */
if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
@ -8553,7 +8553,7 @@ following_call (rtx insn)
will adhere to those rules.
So, late in the compilation process we find all the jump tables, and
expand them into real code -- eg each entry in the jump table vector
expand them into real code -- e.g. each entry in the jump table vector
will get an appropriate label followed by a jump to the final target.
Reorg and the final jump pass can then optimize these branches and

2
gcc/config/pa/pa64-regs.h
View file

@ -146,7 +146,7 @@ Boston, MA 02111-1307, USA. */
but can be less for certain modes in special long registers.
For PA64, GPRs and FPRs hold 64 bits worth (we ignore the 32bit
addressability of the FPRs). ie, we pretend each register holds
addressability of the FPRs). i.e., we pretend each register holds
precisely WORD_SIZE bits. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

2
gcc/config/pdp11/pdp11.c
View file

@ -1691,7 +1691,7 @@ output_addr_const_pdp11 (FILE *file, rtx x)
break;
case PLUS:
/* Some assemblers need integer constants to appear last (eg masm). */
/* Some assemblers need integer constants to appear last (e.g. masm). */
if (GET_CODE (XEXP (x, 0)) == CONST_INT)
{
output_addr_const_pdp11 (file, XEXP (x, 1));

4
gcc/config/rs6000/rs6000.c
View file

@ -11448,7 +11448,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
if (j == nregs)
j = 0;
/* If compiler already emited move of first word by
/* If compiler already emitted move of first word by
store with update, no need to do anything. */
if (j == 0 && used_update)
continue;
@ -11605,7 +11605,7 @@ compute_save_world_info(rs6000_stack_t *info_ptr)
info_ptr->vrsave_mask = compute_vrsave_mask ();
/* Because the Darwin register save/restore routines only handle
F14 .. F31 and V20 .. V31 as per the ABI, perform a consistancy
F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
check and abort if there's something worng. */
if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
|| info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)

2
gcc/config/sh/symbian.c
View file

@ -205,7 +205,7 @@ sh_symbian_dllimport_name_p (const char *symbol)
}
/* Mark a DECL as being dllexport'd.
Note that we override the previous setting (eg: dllimport). */
Note that we override the previous setting (e.g.: dllimport). */
static void
sh_symbian_mark_dllexport (tree decl)

2
gcc/config/sparc/sparc.h
View file

@ -884,7 +884,7 @@ if (TARGET_ARCH64 \
SPARC has 32 integer registers and 32 floating point registers.
64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
accessible. We still account for them to simplify register computations
(eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
(e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
32+32+32+4 == 100.
Register 100 is used as the integer condition code register.
Register 101 is used as the soft frame pointer register. */