arm.c (arm_use_dfa_pipeline_interface): Declare.
2003-06-02 Ben Elliston <bje@wasabisystems.com> * config/arm/arm.c (arm_use_dfa_pipeline_interface): Declare. (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define if not already defined. (arm_use_dfa_pipeline_interface): Implement. * config/arm/arm.md (arm): New automaton. (write_buf): Remove function units; new cpu unit. (write_blockage): Remove function units; new cpu unit. (core): Remove function units; new cpu unit. (r_mem_f_wbuf): New instruction reservation. (store1_wbuf, store2_wbuf, store3_wbuf, store4_wbuf): Likewise. (store1_ldsched, store2, store3, store4): Likewise. (load_ldsched, load_ldsched_xscale, load_or_store): Likewise. (mult, mult_ldsched, mult_ldsched_strongarm): Likewise. (multi_cycle, single_cycle): Likewise. * config/arm/fpa.md (armfp): New automaton. (fpa): Remove function units; new cpu unit. (fpa_mem): Remove function unit; new cpu unit. (fdivx, fdivd, fdivs, fmul, ffmul, farith, ffarith): New reservations. (r_2_f, f_2_r, f_load, f_store, r_mem_f, f_mem_r): Likewise. From-SVN: r67322
This commit is contained in:
Ben Elliston
Ben Elliston
parent
3ae1d4c240
commit
103fc15d39
4 changed files with 170 additions and 105 deletions
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@ -1,3 +1,24 @@
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2003-06-02 Ben Elliston <bje@wasabisystems.com>
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* config/arm/arm.c (arm_use_dfa_pipeline_interface): Declare.
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(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define if not already defined.
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(arm_use_dfa_pipeline_interface): Implement.
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* config/arm/arm.md (arm): New automaton.
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(write_buf): Remove function units; new cpu unit.
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(write_blockage): Remove function units; new cpu unit.
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(core): Remove function units; new cpu unit.
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(r_mem_f_wbuf): New instruction reservation.
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(store1_wbuf, store2_wbuf, store3_wbuf, store4_wbuf): Likewise.
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(store1_ldsched, store2, store3, store4): Likewise.
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(load_ldsched, load_ldsched_xscale, load_or_store): Likewise.
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(mult, mult_ldsched, mult_ldsched_strongarm): Likewise.
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(multi_cycle, single_cycle): Likewise.
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* config/arm/fpa.md (armfp): New automaton.
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(fpa): Remove function units; new cpu unit.
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(fpa_mem): Remove function unit; new cpu unit.
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(fdivx, fdivd, fdivs, fmul, ffmul, farith, ffarith): New reservations.
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(r_2_f, f_2_r, f_load, f_store, r_mem_f, f_mem_r): Likewise.
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2003-06-01 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
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* builtin-attrs.def (ATTR_ASM_FPRINTF): New.
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@ -127,6 +127,7 @@ static void thumb_output_function_prologue PARAMS ((FILE *, Hint));
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static int arm_comp_type_attributes PARAMS ((tree, tree));
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static void arm_set_default_type_attributes PARAMS ((tree));
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static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int));
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static int arm_use_dfa_pipeline_interface PARAMS ((void));
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static int count_insns_for_constant PARAMS ((Hint, int));
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static int arm_get_strip_length PARAMS ((int));
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static bool arm_function_ok_for_sibcall PARAMS ((tree, tree));
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@ -193,6 +194,9 @@ static void aof_globalize_label PARAMS ((FILE *, Ccstar));
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#undef TARGET_SCHED_ADJUST_COST
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#define TARGET_SCHED_ADJUST_COST arm_adjust_cost
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#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
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#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
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#undef TARGET_ENCODE_SECTION_INFO
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#ifdef ARM_PE
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#define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
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@ -3468,6 +3472,12 @@ arm_address_cost (X)
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return (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X));
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}
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static int
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arm_use_dfa_pipeline_interface ()
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{
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return true;
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}
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static int
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arm_adjust_cost (insn, link, dep, cost)
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rtx insn;
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@ -249,12 +249,10 @@
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;; distant label. Only applicable to Thumb code.
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(define_attr "far_jump" "yes,no" (const_string "no"))
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;; (define_function_unit {name} {num-units} {n-users} {test}
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;; {ready-delay} {issue-delay} [{conflict-list}])
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(define_automaton "arm")
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;;--------------------------------------------------------------------
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;; Write buffer
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;;--------------------------------------------------------------------
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;
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; Strictly, we should model a 4-deep write buffer for ARM7xx based chips
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;
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; The write buffer on some of the arm6 processors is hard to model exactly.
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@ -266,102 +264,101 @@
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; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous
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; (they aren't allowed to be at present) then there is a startup cost of 1MCLK
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; cycle to add as well.
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(define_cpu_unit "write_buf" "arm")
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(define_function_unit "write_buf" 1 2
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store1,r_mem_f")) 5 3)
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(define_function_unit "write_buf" 1 2
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store2")) 7 4)
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(define_function_unit "write_buf" 1 2
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store3")) 9 5)
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(define_function_unit "write_buf" 1 2
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store4")) 11 6)
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;;--------------------------------------------------------------------
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;; Write blockage unit
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;;--------------------------------------------------------------------
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;
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; The write_blockage unit models (partially), the fact that reads will stall
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; until the write buffer empties.
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; The f_mem_r and r_mem_f could also block, but they are to the stack,
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; so we don't model them here
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(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store1")) 5 5
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[(eq_attr "write_conflict" "yes")])
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(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store2")) 7 7
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[(eq_attr "write_conflict" "yes")])
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(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store3")) 9 9
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[(eq_attr "write_conflict" "yes")])
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(define_function_unit "write_blockage" 1 0
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(and (eq_attr "model_wbuf" "yes") (eq_attr "type" "store4")) 11 11
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[(eq_attr "write_conflict" "yes")])
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(define_function_unit "write_blockage" 1 0
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "write_conflict" "yes")) 1 1)
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(define_cpu_unit "write_blockage" "arm")
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;;--------------------------------------------------------------------
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;; Core unit
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;;--------------------------------------------------------------------
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; Everything must spend at least one cycle in the core unit
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(define_function_unit "core" 1 0 (eq_attr "core_cycles" "single") 1 1)
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;; Core
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;
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(define_cpu_unit "core" "arm")
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(define_function_unit "core" 1 0
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(and (eq_attr "ldsched" "yes") (eq_attr "type" "store1")) 1 1)
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(define_insn_reservation "r_mem_f_wbuf" 5
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "r_mem_f"))
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"core+write_buf*3")
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(define_function_unit "core" 1 0
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(and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) 2 1)
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(define_insn_reservation "store1_wbuf" 5
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store1"))
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"core+write_buf*3+write_blockage*5")
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;; We do not need to conditionalize the define_function_unit immediately
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;; above. This one will be ignored for anything other than xscale
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;; compiles and for xscale compiles it provides a larger delay
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;; and the scheduler will DTRT.
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;; FIXME: this test needs to be revamped to not depend on this feature
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;; of the scheduler.
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(define_insn_reservation "store2_wbuf" 7
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store2"))
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"core+write_buf*4+write_blockage*7")
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(define_function_unit "core" 1 0
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(define_insn_reservation "store3_wbuf" 9
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store3"))
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"core+write_buf*5+write_blockage*9")
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(define_insn_reservation "store4_wbuf" 11
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(and (eq_attr "model_wbuf" "yes")
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(eq_attr "type" "store4"))
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"core+write_buf*6+write_blockage*11")
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(define_insn_reservation "store2" 3
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(and (eq_attr "model_wbuf" "no")
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(eq_attr "type" "store2"))
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"core*3")
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(define_insn_reservation "store3" 4
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(and (eq_attr "model_wbuf" "no")
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(eq_attr "type" "store3"))
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"core*4")
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(define_insn_reservation "store4" 5
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(and (eq_attr "model_wbuf" "no")
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(eq_attr "type" "store4"))
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"core*5")
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(define_insn_reservation "store1_ldsched" 1
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(and (eq_attr "ldsched" "yes") (eq_attr "type" "store1"))
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"core")
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(define_insn_reservation "load_ldsched_xscale" 3
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(and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load"))
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(eq_attr "is_xscale" "yes"))
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3 1)
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"core")
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(define_function_unit "core" 1 0
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(and (eq_attr "ldsched" "!yes") (eq_attr "type" "load,store1")) 2 2)
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(define_insn_reservation "load_ldsched" 2
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(and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load"))
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(eq_attr "is_xscale" "no"))
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"core")
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(define_function_unit "core" 1 0
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load")) 3 3)
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(define_insn_reservation "load_or_store" 2
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(and (eq_attr "ldsched" "!yes") (eq_attr "type" "load,store1"))
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"core*2")
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(define_function_unit "core" 1 0
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store")) 4 4)
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(define_insn_reservation "mult" 16
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(and (eq_attr "ldsched" "no") (eq_attr "type" "mult"))
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"core*16")
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(define_function_unit "core" 1 0
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")) 6 6)
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(define_function_unit "core" 1 0
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r")) 7 7)
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(define_function_unit "core" 1 0
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(and (eq_attr "ldsched" "no") (eq_attr "type" "mult")) 16 16)
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(define_function_unit "core" 1 0
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(and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "no"))
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(eq_attr "type" "mult")) 4 4)
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(define_function_unit "core" 1 0
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(define_insn_reservation "mult_ldsched_strongarm" 3
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(and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "yes"))
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(eq_attr "type" "mult")) 3 2)
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(eq_attr "type" "mult"))
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"core*2")
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(define_function_unit "core" 1 0 (eq_attr "type" "store2") 3 3)
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(define_insn_reservation "mult_ldsched" 4
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(and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "no"))
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(eq_attr "type" "mult"))
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"core*4")
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(define_function_unit "core" 1 0 (eq_attr "type" "store3") 4 4)
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(define_function_unit "core" 1 0 (eq_attr "type" "store4") 5 5)
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(define_function_unit "core" 1 0
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(define_insn_reservation "multi_cycle" 32
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(and (eq_attr "core_cycles" "multi")
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(eq_attr "type" "!mult,load,store1,store2,store3,store4")) 32 32)
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(eq_attr "type" "!mult,load,store1,store2,store3,store4"))
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"core*32")
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(define_insn_reservation "single_cycle" 1
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(eq_attr "core_cycles" "single")
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"core")
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;;---------------------------------------------------------------------------
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;; Insn patterns
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@ -22,43 +22,80 @@
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA.
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;;--------------------------------------------------------------------
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;; FPA automaton.
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(define_automaton "armfp")
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;; Floating point unit (FPA)
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;;--------------------------------------------------------------------
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fdivx")) 71 69)
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(define_cpu_unit "fpa" "armfp")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fdivd")) 59 57)
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; The fpa10 doesn't really have a memory read unit, but it can start
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; to speculatively execute the instruction in the pipeline, provided
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; the data is already loaded, so pretend reads have a delay of 2 (and
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; that the pipeline is infinite).
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(define_cpu_unit "fpa_mem" "arm")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fdivs")) 31 29)
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(define_insn_reservation "fdivx" 71
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fdivx"))
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"core+fpa*69")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fmul")) 9 7)
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(define_insn_reservation "fdivd" 59
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fdivd"))
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"core+fpa*57")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "ffmul")) 6 4)
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(define_insn_reservation "fdivs" 31
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fdivs"))
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"core+fpa*29")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "farith")) 4 2)
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(define_insn_reservation "fmul" 9
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "fmul"))
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"core+fpa*7")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "ffarith")) 2 2)
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(define_insn_reservation "ffmul" 6
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "ffmul"))
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"core+fpa*4")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "r_2_f")) 5 3)
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(define_insn_reservation "farith" 4
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "farith"))
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"core+fpa*2")
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(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "f_2_r")) 1 2)
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(define_insn_reservation "ffarith" 2
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "ffarith"))
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"core+fpa*2")
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; The fpa10 doesn't really have a memory read unit, but it can start to
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; speculatively execute the instruction in the pipeline, provided the data
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; is already loaded, so pretend reads have a delay of 2 (and that the
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; pipeline is infinite).
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(define_insn_reservation "r_2_f" 5
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "r_2_f"))
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"core+fpa*3")
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(define_insn_reservation "f_2_r" 1
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(and (eq_attr "fpu" "fpa")
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(eq_attr "type" "f_2_r"))
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"core+fpa*2")
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(define_insn_reservation "f_load" 3
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load"))
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"fpa_mem+core*3")
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(define_insn_reservation "f_store" 4
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store"))
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"core*4")
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(define_insn_reservation "r_mem_f" 6
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(and (eq_attr "model_wbuf" "no")
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")))
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"core*6")
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(define_insn_reservation "f_mem_r" 7
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(and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r"))
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"core*7")
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(define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa")
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(eq_attr "type" "f_load")) 3 1)
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(define_insn "*addsf3_fpa"
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[(set (match_operand:SF 0 "s_register_operand" "=f,f")
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