rs6000: Delete "wJ" and "wK" constraints
This replaces "wJ" by "wI", and "wK by "wH", both with isa "p9v". * config/rs6000/constraints.md (define_register_constraint "wJ"): Delete. (define_register_constraint "wK"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wJ and RS6000_CONSTRAINT_wK. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wJ" constraint by "wI" with "p9v". Replace "wK" constraint by "wH" with "p9v". * config/rs6000/vsx.md: Ditto. * doc/md.texi (Machine Constraints): Adjust. From-SVN: r271387
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
d17fbef89f
commit
0c8ac746d1
7 changed files with 109 additions and 99 deletions
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@ -1,3 +1,17 @@
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2019-05-19 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/constraints.md (define_register_constraint "wJ"):
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Delete.
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(define_register_constraint "wK"): Delete.
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* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
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RS6000_CONSTRAINT_wJ and RS6000_CONSTRAINT_wK.
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* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
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(rs6000_init_hard_regno_mode_ok): Adjust.
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* config/rs6000/rs6000.md: Replace "wJ" constraint by "wI" with "p9v".
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Replace "wK" constraint by "wH" with "p9v".
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* config/rs6000/vsx.md: Ditto.
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* doc/md.texi (Machine Constraints): Adjust.
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2019-05-19 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/constraints.md (define_register_constraint "wb"):
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@ -157,12 +157,6 @@
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(define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]"
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"FPR register to hold 32-bit integers or NO_REGS.")
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(define_register_constraint "wJ" "rs6000_constraints[RS6000_CONSTRAINT_wJ]"
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"FPR register to hold 8/16-bit integers or NO_REGS.")
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(define_register_constraint "wK" "rs6000_constraints[RS6000_CONSTRAINT_wK]"
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"Altivec register to hold 8/16-bit integers or NO_REGS.")
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(define_constraint "wL"
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"Int constant that is the element number mfvsrld accesses in a vector."
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(and (match_code "const_int")
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@ -2532,8 +2532,6 @@ rs6000_debug_reg_global (void)
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"wA reg_class = %s\n"
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"wH reg_class = %s\n"
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"wI reg_class = %s\n"
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"wJ reg_class = %s\n"
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"wK reg_class = %s\n"
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"\n",
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
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@ -2562,9 +2560,7 @@ rs6000_debug_reg_global (void)
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]]);
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nl = "\n";
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for (m = 0; m < NUM_MACHINE_MODES; ++m)
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@ -3192,9 +3188,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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wy - Register class to do ISA 2.07 SF operations.
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wz - Float register if we can do 32-bit unsigned int loads.
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wH - Altivec register if SImode is allowed in VSX registers.
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wI - Float register if SImode is allowed in VSX registers.
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wJ - Float register if QImode/HImode are allowed in VSX registers.
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wK - Altivec register if QImode/HImode are allowed in VSX registers. */
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wI - Float register if SImode is allowed in VSX registers. */
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if (TARGET_HARD_FLOAT)
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{
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@ -3271,11 +3265,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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{
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rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
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rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
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if (TARGET_P9_VECTOR)
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{
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rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
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rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
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}
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}
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/* Set up the reload helper and direct move functions. */
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@ -1273,8 +1273,6 @@ enum r6000_reg_class_enum {
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RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
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RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
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RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
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RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */
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RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */
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RS6000_CONSTRAINT_MAX
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};
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@ -726,15 +726,16 @@
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;; complex forms. Basic data transfer is done later.
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(define_insn "zero_extendqi<mode>2"
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[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wJwK,^wK")
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(zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,wK")))]
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[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wIwH,^wH")
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(zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,wH")))]
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""
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"@
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lbz%U1%X1 %0,%1
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rlwinm %0,%1,0,0xff
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lxsibzx %x0,%y1
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vextractub %0,%1,7"
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[(set_attr "type" "load,shift,fpload,vecperm")])
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[(set_attr "type" "load,shift,fpload,vecperm")
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(set_attr "isa" "*,*,p9v,p9v")])
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(define_insn_and_split "*zero_extendqi<mode>2_dot"
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[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
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@ -779,15 +780,16 @@
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(define_insn "zero_extendhi<mode>2"
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[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wJwK,^wK")
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(zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wK")))]
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[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wIwH,^wH")
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(zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wH")))]
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""
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"@
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lhz%U1%X1 %0,%1
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rlwinm %0,%1,0,0xffff
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lxsihzx %x0,%y1
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vextractuh %0,%1,6"
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[(set_attr "type" "load,shift,fpload,vecperm")])
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[(set_attr "type" "load,shift,fpload,vecperm")
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(set_attr "isa" "*,*,p9v,p9v")])
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(define_insn_and_split "*zero_extendhi<mode>2_dot"
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[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
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@ -832,8 +834,8 @@
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(define_insn "zero_extendsi<mode>2"
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[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wu,wj,r,wJwK")
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(zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wIwH,wJwK")))]
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[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wu,wj,r,wIwH")
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(zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wIwH,wIwH")))]
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""
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"@
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lwz%U1%X1 %0,%1
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@ -843,7 +845,8 @@
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mtvsrwz %x0,%1
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mfvsrwz %0,%x1
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xxextractuw %x0,%x1,4"
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[(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")])
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[(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")
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(set_attr "isa" "*,*,*,*,*,*,p9v")])
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(define_insn_and_split "*zero_extendsi<mode>2_dot"
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[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
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@ -888,13 +891,14 @@
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(define_insn "extendqi<mode>2"
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[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*wK")
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(sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,?*wK")))]
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[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*wH")
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(sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,?*wH")))]
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""
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"@
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extsb %0,%1
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vextsb2d %0,%1"
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[(set_attr "type" "exts,vecperm")])
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[(set_attr "type" "exts,vecperm")
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(set_attr "isa" "*,p9v")])
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(define_insn_and_split "*extendqi<mode>2_dot"
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[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
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@ -945,8 +949,8 @@
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"")
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(define_insn "*extendhi<mode>2"
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[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wK,?*wK")
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(sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wK")))]
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[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wH,?*wH")
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(sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wH")))]
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""
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"@
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lha%U1%X1 %0,%1
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@ -955,7 +959,8 @@
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vextsh2d %0,%1"
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[(set_attr "type" "load,exts,fpload,vecperm")
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(set_attr "sign_extend" "yes")
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(set_attr "length" "4,4,8,4")])
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(set_attr "length" "4,4,8,4")
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(set_attr "isa" "*,*,p9v,p9v")])
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(define_split
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[(set (match_operand:EXTHI 0 "altivec_register_operand")
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@ -1014,10 +1019,10 @@
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(define_insn "extendsi<mode>2"
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[(set (match_operand:EXTSI 0 "gpc_reg_operand"
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"=r, r, wl, wu, wj, wK, wH, wr")
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"=r, r, wl, wu, wj, wH, wH, wr")
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(sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
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"YZ, r, Z, Z, r, wK, wH, ?wIwH")))]
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"YZ, r, Z, Z, r, wH, wH, ?wIwH")))]
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""
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"@
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lwa%U1%X1 %0,%1
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@ -1030,7 +1035,8 @@
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#"
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[(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
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(set_attr "sign_extend" "yes")
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(set_attr "length" "4,4,4,4,4,4,8,8")])
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(set_attr "length" "4,4,4,4,4,4,8,8")
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(set_attr "isa" "*,*,*,*,*,p9v,*,*")])
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(define_split
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[(set (match_operand:EXTSI 0 "int_reg_operand")
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@ -5218,8 +5224,8 @@
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; We don't define lfiwax/lfiwzx with the normal definition, because we
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; don't want to support putting SImode in FPR registers.
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(define_insn "lfiwax"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wK")
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(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wK")]
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[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wH")
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(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wH")]
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UNSPEC_LFIWAX))]
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"TARGET_HARD_FLOAT && TARGET_LFIWAX"
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"@
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@ -5227,7 +5233,8 @@
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lxsiwax %x0,%y1
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mtvsrwa %x0,%1
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vextsw2d %0,%1"
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[(set_attr "type" "fpload,fpload,mffgpr,vecexts")])
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[(set_attr "type" "fpload,fpload,mffgpr,vecexts")
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(set_attr "isa" "*,*,*,p9v")])
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; This split must be run before register allocation because it allocates the
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; memory slot that is needed to move values to/from the FPR. We don't allocate
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@ -5299,8 +5306,8 @@
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(set_attr "type" "fpload")])
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(define_insn "lfiwzx"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wJwK")
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(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wJwK")]
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[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wIwH")
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(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wIwH")]
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UNSPEC_LFIWZX))]
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"TARGET_HARD_FLOAT && TARGET_LFIWZX"
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"@
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@ -5308,7 +5315,8 @@
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lxsiwzx %x0,%y1
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mtvsrwz %x0,%1
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xxextractuw %x0,%x1,4"
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[(set_attr "type" "fpload,fpload,mftgpr,vecexts")])
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[(set_attr "type" "fpload,fpload,mftgpr,vecexts")
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(set_attr "isa" "*,*,*,p9v")])
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(define_insn_and_split "floatunssi<mode>2_lfiwzx"
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[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
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@ -5552,10 +5560,10 @@
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(define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
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[(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
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(float:FP_ISA3
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(match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z")))
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(clobber (match_scratch:DI 2 "=wK,wi,wK"))
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(match_operand:QHI 1 "reg_or_indexed_operand" "wH,r,Z")))
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(clobber (match_scratch:DI 2 "=wH,wi,wH"))
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(clobber (match_scratch:DI 3 "=X,r,X"))
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(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wK"))]
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(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wH"))]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
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"#"
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"&& reload_completed"
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@ -5587,7 +5595,8 @@
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emit_insn (gen_floatdi<FP_ISA3:mode>2 (result, di));
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DONE;
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})
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}
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[(set_attr "isa" "p9v,*,p9v")])
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(define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
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[(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand")
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@ -5604,8 +5613,8 @@
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(define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
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[(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
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(unsigned_float:FP_ISA3
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(match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z")))
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(clobber (match_scratch:DI 2 "=wK,wi,wJwK"))
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(match_operand:QHI 1 "reg_or_indexed_operand" "wH,r,Z")))
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(clobber (match_scratch:DI 2 "=wH,wi,wIwH"))
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(clobber (match_scratch:DI 3 "=X,r,X"))]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
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"#"
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@ -5632,7 +5641,8 @@
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emit_insn (gen_floatdi<FP_ISA3:mode>2 (result, di));
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DONE;
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})
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}
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[(set_attr "isa" "p9v,*,p9v")])
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(define_expand "fix_trunc<mode>si2"
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[(set (match_operand:SI 0 "gpc_reg_operand")
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@ -5745,8 +5755,8 @@
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;; register allocation prevents the register allocator from doing a direct move
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;; of the SImode value to a GPR, and then a store/load.
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(define_insn_and_split "fix<uns>_trunc<SFDF:mode><QHI:mode>2"
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[(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=wJ,wJwK,r")
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(any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wJ,wJwK,wa")))
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[(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=wI,wIwH,r")
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(any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wI,wIwH,wa")))
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(clobber (match_scratch:SI 2 "=X,X,wi"))]
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"TARGET_DIRECT_MOVE"
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"@
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@ -5761,8 +5771,9 @@
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{
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operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]));
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}
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[(set_attr "length" "4,4,8")
|
||||
(set_attr "type" "fp")])
|
||||
[(set_attr "type" "fp")
|
||||
(set_attr "length" "4,4,8")
|
||||
(set_attr "isa" "p9v,p9v,*")])
|
||||
|
||||
(define_insn "*fix<uns>_trunc<SFDF:mode>si2_p8"
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=d,wa")
|
||||
|
|
@ -6871,17 +6882,15 @@
|
|||
[(set (match_operand:SI 0 "nonimmediate_operand"
|
||||
"=r, r, r, wI, wH,
|
||||
m, Z, Z, r, r,
|
||||
r, wIwH, wJwK, wJwK, wu,
|
||||
wJwK, wH, wK, wIwH, r,
|
||||
r, wIwH, wIwH, wIwH, wu,
|
||||
wIwH, wH, wH, wIwH, r,
|
||||
r, *h, *h")
|
||||
|
||||
(match_operand:SI 1 "input_operand"
|
||||
"r, U, m, Z, Z,
|
||||
r, wI, wH, I, L,
|
||||
n, wIwH, O, wM, wB,
|
||||
O, wM, wS, r, wIwH,
|
||||
*h, r, 0"))]
|
||||
|
||||
"gpc_reg_operand (operands[0], SImode)
|
||||
|| gpc_reg_operand (operands[1], SImode)"
|
||||
"@
|
||||
|
|
@ -6914,13 +6923,18 @@
|
|||
*, veclogical, vecsimple, vecsimple, vecsimple,
|
||||
veclogical, veclogical, vecsimple, mffgpr, mftgpr,
|
||||
*, *, *")
|
||||
|
||||
(set_attr "length"
|
||||
"4, 4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4,
|
||||
8, 4, 4, 4, 4,
|
||||
4, 4, 8, 4, 4,
|
||||
4, 4, 4")])
|
||||
4, 4, 4")
|
||||
(set_attr "isa"
|
||||
"*, *, *, *, *,
|
||||
*, *, *, *, *,
|
||||
*, *, p9v, p9v, *,
|
||||
p9v, *, p9v, *, *,
|
||||
*, *, *")])
|
||||
|
||||
;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
|
||||
;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0))
|
||||
|
|
@ -7006,18 +7020,15 @@
|
|||
(define_insn_and_split "*movdi_from_sf_zero_ext"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand"
|
||||
"=r, r, ?*wI, ?*wH, r,
|
||||
?wK, wIwH")
|
||||
|
||||
?wH, wIwH")
|
||||
(zero_extend:DI
|
||||
(unspec:SI [(match_operand:SF 1 "input_operand"
|
||||
"r, m, Z, Z, wIwH,
|
||||
wIwH, r")]
|
||||
UNSPEC_SI_FROM_SF)))
|
||||
|
||||
(clobber (match_scratch:V4SF 2
|
||||
"=X, X, X, X, wa,
|
||||
wIwH, X"))]
|
||||
|
||||
"TARGET_DIRECT_MOVE_64BIT
|
||||
&& (register_operand (operands[0], DImode)
|
||||
|| register_operand (operands[1], SImode))"
|
||||
|
|
@ -7046,10 +7057,12 @@
|
|||
[(set_attr "type"
|
||||
"*, load, fpload, fpload, two,
|
||||
two, mffgpr")
|
||||
|
||||
(set_attr "length"
|
||||
"4, 4, 4, 4, 8,
|
||||
8, 4")])
|
||||
8, 4")
|
||||
(set_attr "isa"
|
||||
"*, *, *, *, *,
|
||||
p9v, *")])
|
||||
|
||||
;; Like movsi_from_sf, but combine a convert from DFmode to SFmode before
|
||||
;; moving it to SImode. We cannot do a SFmode store without having to do the
|
||||
|
|
@ -7143,15 +7156,13 @@
|
|||
;; MTVSRWZ MF%1 MT%1 NOP
|
||||
(define_insn "*mov<mode>_internal"
|
||||
[(set (match_operand:QHI 0 "nonimmediate_operand"
|
||||
"=r, r, wJwK, m, Z, r,
|
||||
wJwK, wJwK, wJwK, wK, ?wK, r,
|
||||
wJwK, r, *c*l, *h")
|
||||
|
||||
"=r, r, wIwH, m, Z, r,
|
||||
wIwH, wIwH, wIwH, wH, ?wH, r,
|
||||
wIwH, r, *c*l, *h")
|
||||
(match_operand:QHI 1 "input_operand"
|
||||
"r, m, Z, r, wJwK, i,
|
||||
wJwK, O, wM, wB, wS, wJwK,
|
||||
"r, m, Z, r, wIwH, i,
|
||||
wIwH, O, wM, wB, wS, wIwH,
|
||||
r, *h, r, 0"))]
|
||||
|
||||
"gpc_reg_operand (operands[0], <MODE>mode)
|
||||
|| gpc_reg_operand (operands[1], <MODE>mode)"
|
||||
"@
|
||||
|
|
@ -7175,11 +7186,14 @@
|
|||
"*, load, fpload, store, fpstore, *,
|
||||
vecsimple, vecperm, vecperm, vecperm, vecperm, mftgpr,
|
||||
mffgpr, mfjmpr, mtjmpr, *")
|
||||
|
||||
(set_attr "length"
|
||||
"4, 4, 4, 4, 4, 4,
|
||||
4, 4, 4, 4, 8, 4,
|
||||
4, 4, 4, 4")])
|
||||
4, 4, 4, 4")
|
||||
(set_attr "isa"
|
||||
"*, *, p9v, *, p9v, *,
|
||||
p9v, p9v, p9v, p9v, p9v, p9v,
|
||||
p9v, *, *, *")])
|
||||
|
||||
|
||||
;; Here is how to move condition codes around. When we store CC data in
|
||||
|
|
|
|||
|
|
@ -3525,7 +3525,7 @@
|
|||
(define_insn "vsx_extract_<mode>_p9"
|
||||
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,<VSX_EX>")
|
||||
(vec_select:<VS_scalar>
|
||||
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
|
||||
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,<VSX_EX>")
|
||||
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
|
||||
(clobber (match_scratch:SI 3 "=r,X"))]
|
||||
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
|
||||
|
|
@ -3550,7 +3550,8 @@
|
|||
return "vextractu<wd> %0,%1,%2";
|
||||
}
|
||||
}
|
||||
[(set_attr "type" "vecsimple")])
|
||||
[(set_attr "type" "vecsimple")
|
||||
(set_attr "isa" "p9v,*")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:<VS_scalar> 0 "int_reg_operand")
|
||||
|
|
@ -3580,7 +3581,7 @@
|
|||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,<VSX_EX>")
|
||||
(zero_extend:DI
|
||||
(vec_select:<VS_scalar>
|
||||
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
|
||||
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,<VSX_EX>")
|
||||
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
|
||||
(clobber (match_scratch:SI 3 "=r,X"))]
|
||||
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
|
||||
|
|
@ -3593,7 +3594,8 @@
|
|||
(clobber (match_dup 3))])]
|
||||
{
|
||||
operands[4] = gen_rtx_REG (<VS_scalar>mode, REGNO (operands[0]));
|
||||
})
|
||||
}
|
||||
[(set_attr "isa" "p9v,*")])
|
||||
|
||||
;; Optimize stores to use the ISA 3.0 scalar store instructions
|
||||
(define_insn_and_split "*vsx_extract_<mode>_store_p9"
|
||||
|
|
@ -3617,9 +3619,9 @@
|
|||
(define_insn_and_split "*vsx_extract_si"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,wHwI,Z")
|
||||
(vec_select:SI
|
||||
(match_operand:V4SI 1 "gpc_reg_operand" "wJv,wJv,wJv")
|
||||
(match_operand:V4SI 1 "gpc_reg_operand" "v,v,v")
|
||||
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))
|
||||
(clobber (match_scratch:V4SI 3 "=wJv,wJv,wJv"))]
|
||||
(clobber (match_scratch:V4SI 3 "=v,v,v"))]
|
||||
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT && !TARGET_P9_VECTOR"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
|
|
@ -3733,7 +3735,7 @@
|
|||
(define_insn_and_split "vsx_extract_<mode>_var"
|
||||
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
|
||||
(unspec:<VS_scalar>
|
||||
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m")
|
||||
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
|
||||
UNSPEC_VSX_EXTRACT))
|
||||
(clobber (match_scratch:DI 3 "=r,r,&b"))
|
||||
|
|
@ -3746,13 +3748,14 @@
|
|||
rs6000_split_vec_extract_var (operands[0], operands[1], operands[2],
|
||||
operands[3], operands[4]);
|
||||
DONE;
|
||||
})
|
||||
}
|
||||
[(set_attr "isa" "p9v,*,*")])
|
||||
|
||||
(define_insn_and_split "*vsx_extract_<mode>_<VS_scalar>mode_var"
|
||||
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
|
||||
(zero_extend:<VS_scalar>
|
||||
(unspec:<VSX_EXTRACT_I:VS_scalar>
|
||||
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wK,v,m")
|
||||
[(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
|
||||
UNSPEC_VSX_EXTRACT)))
|
||||
(clobber (match_scratch:DI 3 "=r,r,&b"))
|
||||
|
|
@ -3767,7 +3770,8 @@
|
|||
operands[1], operands[2],
|
||||
operands[3], operands[4]);
|
||||
DONE;
|
||||
})
|
||||
}
|
||||
[(set_attr "isa" "p9v,*,*")])
|
||||
|
||||
;; VSX_EXTRACT optimizations
|
||||
;; Optimize double d = (double) vec_extract (vi, <n>)
|
||||
|
|
@ -3951,7 +3955,7 @@
|
|||
(match_operand:SF 2 "gpc_reg_operand" "ww")
|
||||
(match_operand:QI 3 "const_0_to_3_operand" "n")]
|
||||
UNSPEC_VSX_SET))
|
||||
(clobber (match_scratch:SI 4 "=&wJwK"))]
|
||||
(clobber (match_scratch:SI 4 "=&wIwH"))]
|
||||
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
|
|
@ -3976,7 +3980,8 @@
|
|||
operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
|
||||
}
|
||||
[(set_attr "type" "vecperm")
|
||||
(set_attr "length" "12")])
|
||||
(set_attr "length" "12")
|
||||
(set_attr "isa" "p9v")])
|
||||
|
||||
;; Special case setting 0.0f to a V4SF element
|
||||
(define_insn_and_split "*vsx_set_v4sf_p9_zero"
|
||||
|
|
@ -3986,7 +3991,7 @@
|
|||
(match_operand:SF 2 "zero_fp_constant" "j")
|
||||
(match_operand:QI 3 "const_0_to_3_operand" "n")]
|
||||
UNSPEC_VSX_SET))
|
||||
(clobber (match_scratch:SI 4 "=&wJwK"))]
|
||||
(clobber (match_scratch:SI 4 "=&wIwH"))]
|
||||
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
|
|
@ -4001,7 +4006,8 @@
|
|||
operands[5] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
|
||||
}
|
||||
[(set_attr "type" "vecperm")
|
||||
(set_attr "length" "8")])
|
||||
(set_attr "length" "8")
|
||||
(set_attr "isa" "p9v")])
|
||||
|
||||
;; Optimize x = vec_insert (vec_extract (v2, n), v1, m) if n is the element
|
||||
;; that is in the default scalar position (1 for big endian, 2 for little
|
||||
|
|
@ -4043,7 +4049,7 @@
|
|||
[(match_operand:QI 3 "const_0_to_3_operand" "n")]))
|
||||
(match_operand:QI 4 "const_0_to_3_operand" "n")]
|
||||
UNSPEC_VSX_SET))
|
||||
(clobber (match_scratch:SI 5 "=&wJwK"))]
|
||||
(clobber (match_scratch:SI 5 "=&wIwH"))]
|
||||
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
|
||||
&& TARGET_P9_VECTOR && TARGET_POWERPC64
|
||||
&& (INTVAL (operands[3]) != (BYTES_BIG_ENDIAN ? 1 : 2))"
|
||||
|
|
@ -4066,7 +4072,8 @@
|
|||
operands[7] = gen_lowpart (V4SImode, operands[0]);
|
||||
operands[8] = gen_lowpart (V4SImode, operands[1]);
|
||||
}
|
||||
[(set_attr "type" "vecperm")])
|
||||
[(set_attr "type" "vecperm")
|
||||
(set_attr "isa" "p9v")])
|
||||
|
||||
;; Expanders for builtins
|
||||
(define_expand "vsx_mergel_<mode>"
|
||||
|
|
|
|||
|
|
@ -3337,12 +3337,6 @@ Altivec register if @option{-mvsx-small-integer}.
|
|||
@item wI
|
||||
Floating point register if @option{-mvsx-small-integer}.
|
||||
|
||||
@item wJ
|
||||
FP register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
|
||||
|
||||
@item wK
|
||||
Altivec register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
|
||||
|
||||
@item wL
|
||||
Int constant that is the element number that the MFVSRLD instruction.
|
||||
targets.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue