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Fix target/68124

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PR target/68124
        PR rtl-opt/67609
        * config/i386/i386.c (ix86_cannot_change_mode_class): Tighten
        sse check to the exact conditions of PR 67609.

From-SVN: r229550
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Richard Henderson 2015-10-29 11:36:39 -07:00 • committed by Richard Henderson
parent d8cf6ce752
commit 0bb7645daa
2 changed files with 28 additions and 15 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2015-10-29 Richard Henderson <rth@redhat.com>
PR target/68124
PR rtl-opt/67609
* config/i386/i386.c (ix86_cannot_change_mode_class): Tighten
sse check to the exact conditions of PR 67609.
2015-10-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_init_libfuncs): Split libfunc

36
gcc/config/i386/i386.c
View file

@ -43031,22 +43031,28 @@ ix86_cannot_change_mode_class (machine_mode from, machine_mode to,
if (MAYBE_FLOAT_CLASS_P (regclass))
return true;
/* Vector registers do not support QI or HImode loads. If we don't
disallow a change to these modes, reload will assume it's ok to
drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
the vec_dupv4hi pattern.
Further, we cannot allow word_mode subregs of full vector modes.
Otherwise the middle-end will assume it's ok to store to
(subreg:DI (reg:TI 100) 0) in order to modify only the low 64 bits
of the 128-bit register. However, after reload the subreg will
be dropped leaving a plain DImode store. This is indistinguishable
from a "normal" DImode move, and so we're justified to use movsd,
which modifies the entire 128-bit register.
Combining these two conditions, disallow all narrowing mode changes. */
if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
return GET_MODE_SIZE (to) < GET_MODE_SIZE (from);
{
int from_size = GET_MODE_SIZE (from);
int to_size = GET_MODE_SIZE (to);
/* Vector registers do not support QI or HImode loads. If we don't
disallow a change to these modes, reload will assume it's ok to
drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
the vec_dupv4hi pattern. */
if (from_size < 4)
return true;
/* Further, we cannot allow word_mode subregs of full vector modes.
Otherwise the middle-end will assume it's ok to store to
(subreg:DI (reg:TI 100) 0) in order to modify only the low 64 bits
of the 128-bit register. However, after reload the subreg will
be dropped leaving a plain DImode store. This is indistinguishable
from a "normal" DImode move, and so we're justified to use movsd,
which modifies the entire 128-bit register. */
if (to_size == UNITS_PER_WORD && from_size > UNITS_PER_WORD)
return true;
}
return false;
}