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re PR rtl-optimization/48143 (ICE: in reset_sched_cycles_in_current_ebb, at sel-sched.c:7114 with custom flags)

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PR rtl-optimization/48143
        * config/i386/sse.md (*sse2_cvtpd2dq): Add athlon_decode attribute.
        (*sse2_cvttpd2dq, sse2_cvtss2sd, *sse2_cvtpd2ps,
        sse2_cvtps2pd): Likewise.

From-SVN: r171286
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Andrey Belevantsev 2011-03-22 15:33:53 +03:00 • committed by Andrey Belevantsev
parent d89afca5b4
commit 0b7e851b85
2 changed files with 12 additions and 0 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2011-03-22 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/48143
* config/i386/sse.md (*sse2_cvtpd2dq): Add athlon_decode attribute.
(*sse2_cvttpd2dq, sse2_cvtss2sd, *sse2_cvtpd2ps,
sse2_cvtps2pd): Likewise.
2011-03-22 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* recog.c (canonicalize_change_group): Use validate_unshare_change.

5
gcc/config/i386/sse.md
View file

@ -2715,6 +2715,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")
(set_attr "athlon_decode" "vector")
(set_attr "bdver1_decode" "double")])
(define_insn "avx_cvttpd2dq256"
@ -2746,6 +2747,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")
(set_attr "amdfam10_decode" "double")
(set_attr "athlon_decode" "vector")
(set_attr "bdver1_decode" "double")])
(define_insn "*avx_cvtsd2ss"
@ -2806,6 +2808,7 @@
"cvtss2sd\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "athlon_decode" "direct,direct")
(set_attr "bdver1_decode" "direct,direct")
(set_attr "mode" "DF")])
@ -2842,6 +2845,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "V4SF")
(set_attr "amdfam10_decode" "double")
(set_attr "athlon_decode" "vector")
(set_attr "bdver1_decode" "double")])
(define_insn "avx_cvtps2pd256"
@ -2879,6 +2883,7 @@
(set_attr "mode" "V2DF")
(set_attr "prefix_data16" "0")
(set_attr "amdfam10_decode" "direct")
(set_attr "athlon_decode" "double")
(set_attr "bdver1_decode" "double")])
(define_expand "vec_unpacks_hi_v4sf"