rs6000-c.c (altivec_overloaded_builtins): Add Cell Altivec intrinsics.
2008-10-01 Andrew Pinski <andrew_pinski@playstation.sony.com>
Yukishige Shibata <shibata@rd.scei.sony.co.jp>
Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add Cell
Altivec intrinsics.
* config/rs6000/rs6000.c (altivec_expand_lv_builtin): Delete
prototype. Add new parameter, blk.
Use BLKmode for the MEM if blk is true.
(altivec_expand_builtin): Handle ALTIVEC_BUILTIN_STVLX,
ALTIVEC_BUILTIN_STVLXL, ALTIVEC_BUILTIN_STVRX, and
ALTIVEC_BUILTIN_STVRXL.
Update usage of altivec_expand_lv_builtin.
Handle ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL,
ALTIVEC_BUILTIN_LVRX, and ALTIVEC_BUILTIN_LVRXL.
(altivec_init_builtins): If compiling for the Cell, also define the
cell VMX builtins.
* config/rs6000/rs6000.h (rs6000_builtins): Define
ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL, ALTIVEC_BUILTIN_LVRX,
ALTIVEC_BUILTIN_LVRXL, ALTIVEC_BUILTIN_STVLX, ALTIVEC_BUILTIN_STVLXL,
ALTIVEC_BUILTIN_STVRX, ALTIVEC_BUILTIN_STVRXL,
ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_VEC_LVLXL,
ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_VEC_LVRXL,
ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_VEC_STVLXL,
ALTIVEC_BUILTIN_VEC_STVRX, and ALTIVEC_BUILTIN_VEC_STVRXL.
* config/rs6000/altivec.md (define_constants): Define UNSPEC_LVLX,
UNSPEC_LVLXL, UNSPEC_LVRX, UNSPEC_LVRXL, UNSPEC_STVLX, UNSPEC_STVLXL,
UNSPEC_STVRX, and UNSPEC_STVRXL.
(altivec_lvlx): New pattern.
(altivec_lvlxl): New pattern.
(altivec_lvrx): New pattern.
(altivec_lvrxl): New pattern.
(altivec_stvlx): New pattern.
(altivec_stvlxl): New pattern.
(altivec_stvrx): New pattern.
(altivec_stvrxl): New pattern.
* config/rs6000/altivec.h (vec_lvlx): Define if PPU is defined.
(vec_lvlxl): Likewise.
(vec_lvrx): Define if PPU is defined.
(vec_lvrxl): Likewise.
(vec_stvlx): Define if PPU is defined.
(vec_stvlxl): Likewise.
(vec_stvrx): Define if PPU is defined.
(vec_stvrxl): Likewise.
2008-10-01 Andrew Pinski <andrew_pinski@playstation.sony.com>
* gcc.target/powerpc/altivec_check.h (altivec_cell_check): New function.
* gcc.target/powerpc/altivec-cell-6.c: New test.
* gcc.target/powerpc/altivec-cell-7.c: New test.
* gcc.target/powerpc/altivec-cell-8.c: New test.
From-SVN: r140820
This commit is contained in:
Andrew Pinski
parent
522aa637e4
commit
0b61703ca6
11 changed files with 618 additions and 18 deletions
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@ -1,3 +1,48 @@
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2008-10-01 Andrew Pinski <andrew_pinski@playstation.sony.com>
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Yukishige Shibata <shibata@rd.scei.sony.co.jp>
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Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
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* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add Cell
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Altivec intrinsics.
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* config/rs6000/rs6000.c (altivec_expand_lv_builtin): Delete
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prototype. Add new parameter, blk.
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Use BLKmode for the MEM if blk is true.
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(altivec_expand_builtin): Handle ALTIVEC_BUILTIN_STVLX,
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ALTIVEC_BUILTIN_STVLXL, ALTIVEC_BUILTIN_STVRX, and
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ALTIVEC_BUILTIN_STVRXL.
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Update usage of altivec_expand_lv_builtin.
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Handle ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL,
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ALTIVEC_BUILTIN_LVRX, and ALTIVEC_BUILTIN_LVRXL.
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(altivec_init_builtins): If compiling for the Cell, also define the
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cell VMX builtins.
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* config/rs6000/rs6000.h (rs6000_builtins): Define
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ALTIVEC_BUILTIN_LVLX, ALTIVEC_BUILTIN_LVLXL, ALTIVEC_BUILTIN_LVRX,
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ALTIVEC_BUILTIN_LVRXL, ALTIVEC_BUILTIN_STVLX, ALTIVEC_BUILTIN_STVLXL,
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ALTIVEC_BUILTIN_STVRX, ALTIVEC_BUILTIN_STVRXL,
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ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_VEC_LVLXL,
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ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_VEC_LVRXL,
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ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_VEC_STVLXL,
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ALTIVEC_BUILTIN_VEC_STVRX, and ALTIVEC_BUILTIN_VEC_STVRXL.
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* config/rs6000/altivec.md (define_constants): Define UNSPEC_LVLX,
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UNSPEC_LVLXL, UNSPEC_LVRX, UNSPEC_LVRXL, UNSPEC_STVLX, UNSPEC_STVLXL,
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UNSPEC_STVRX, and UNSPEC_STVRXL.
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(altivec_lvlx): New pattern.
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(altivec_lvlxl): New pattern.
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(altivec_lvrx): New pattern.
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(altivec_lvrxl): New pattern.
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(altivec_stvlx): New pattern.
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(altivec_stvlxl): New pattern.
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(altivec_stvrx): New pattern.
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(altivec_stvrxl): New pattern.
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* config/rs6000/altivec.h (vec_lvlx): Define if PPU is defined.
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(vec_lvlxl): Likewise.
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(vec_lvrx): Define if PPU is defined.
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(vec_lvrxl): Likewise.
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(vec_stvlx): Define if PPU is defined.
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(vec_stvlxl): Likewise.
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(vec_stvrx): Define if PPU is defined.
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(vec_stvrxl): Likewise.
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2008-10-01 Geert Bosch <bosch@adacore.com>
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* tree.c (contains_placeholder_p): Return 0 for a SAVE_EXPR.
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@ -10,10 +55,10 @@
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2008-10-01 Richard Guenther <rguenther@suse.de>
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PR middle-end/37285
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* tree-vrp.c (execute_vrp): If we optimized away the default
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case make sure to promote the label that got in place of it
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to a default case label.
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PR middle-end/37285
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* tree-vrp.c (execute_vrp): If we optimized away the default
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case make sure to promote the label that got in place of it
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to a default case label.
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2008-10-01 Richard Henderson <rth@redhat.com>
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@ -220,7 +265,7 @@
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2008-09-26 Vladimir Makarov <vmakarov@redhat.com>
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Revert:
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2008-09-25 Vladimir Makarov <vmakarov@redhat.com>
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2008-09-25 Vladimir Makarov <vmakarov@redhat.com>
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* ira-lives.c:...
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* doc/rtl.texi:...
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@ -205,6 +205,13 @@
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#define vec_lvebx __builtin_vec_lvebx
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#define vec_lvehx __builtin_vec_lvehx
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#define vec_lvewx __builtin_vec_lvewx
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/* Cell only intrinsics. */
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#ifdef __PPU__
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#define vec_lvlx __builtin_vec_lvlx
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#define vec_lvlxl __builtin_vec_lvlxl
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#define vec_lvrx __builtin_vec_lvrx
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#define vec_lvrxl __builtin_vec_lvrxl
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#endif
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#define vec_lvsl __builtin_vec_lvsl
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#define vec_lvsr __builtin_vec_lvsr
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#define vec_max __builtin_vec_max
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@ -239,6 +246,13 @@
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#define vec_stvebx __builtin_vec_stvebx
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#define vec_stvehx __builtin_vec_stvehx
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#define vec_stvewx __builtin_vec_stvewx
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/* Cell only intrinsics. */
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#ifdef __PPU__
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#define vec_stvlx __builtin_vec_stvlx
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#define vec_stvlxl __builtin_vec_stvlxl
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#define vec_stvrx __builtin_vec_stvrx
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#define vec_stvrxl __builtin_vec_stvrxl
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#endif
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#define vec_sub __builtin_vec_sub
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#define vec_subs __builtin_vec_subs
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#define vec_sum __builtin_vec_sum
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@ -130,6 +130,14 @@
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(UNSPEC_INTERLO_V8HI 233)
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(UNSPEC_INTERLO_V16QI 234)
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(UNSPEC_INTERLO_V4SF 235)
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(UNSPEC_LVLX 236)
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(UNSPEC_LVLXL 237)
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(UNSPEC_LVRX 238)
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(UNSPEC_LVRXL 239)
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(UNSPEC_STVLX 240)
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(UNSPEC_STVLXL 241)
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(UNSPEC_STVRX 242)
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(UNSPEC_STVRXL 243)
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(UNSPEC_VMULWHUB 308)
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(UNSPEC_VMULWLUB 309)
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(UNSPEC_VMULWHSB 310)
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@ -2677,6 +2685,76 @@
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DONE;
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}")
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;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
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;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
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(define_insn "altivec_lvlx"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
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UNSPEC_LVLX))]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"lvlx %0,%y1"
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[(set_attr "type" "vecload")])
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(define_insn "altivec_lvlxl"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
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UNSPEC_LVLXL))]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"lvlxl %0,%y1"
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[(set_attr "type" "vecload")])
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(define_insn "altivec_lvrx"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
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UNSPEC_LVRX))]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"lvrx %0,%y1"
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[(set_attr "type" "vecload")])
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(define_insn "altivec_lvrxl"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
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UNSPEC_LVRXL))]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"lvrxl %0,%y1"
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[(set_attr "type" "vecload")])
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(define_insn "altivec_stvlx"
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[(parallel
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[(set (match_operand:V4SI 0 "memory_operand" "=Z")
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(match_operand:V4SI 1 "register_operand" "v"))
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(unspec [(const_int 0)] UNSPEC_STVLX)])]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"stvlx %1,%y0"
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[(set_attr "type" "vecstore")])
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(define_insn "altivec_stvlxl"
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[(parallel
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[(set (match_operand:V4SI 0 "memory_operand" "=Z")
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(match_operand:V4SI 1 "register_operand" "v"))
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(unspec [(const_int 0)] UNSPEC_STVLXL)])]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"stvlxl %1,%y0"
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[(set_attr "type" "vecstore")])
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(define_insn "altivec_stvrx"
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[(parallel
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[(set (match_operand:V4SI 0 "memory_operand" "=Z")
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(match_operand:V4SI 1 "register_operand" "v"))
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(unspec [(const_int 0)] UNSPEC_STVRX)])]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"stvrx %1,%y0"
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[(set_attr "type" "vecstore")])
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(define_insn "altivec_stvrxl"
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[(parallel
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[(set (match_operand:V4SI 0 "memory_operand" "=Z")
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(match_operand:V4SI 1 "register_operand" "v"))
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(unspec [(const_int 0)] UNSPEC_STVRXL)])]
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"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
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"stvrxl %1,%y0"
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[(set_attr "type" "vecstore")])
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(define_expand "vec_extract_evenv4si"
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[(set (match_operand:V4SI 0 "register_operand" "")
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(unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
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@ -996,6 +996,150 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
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{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
|
||||
RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
|
||||
|
|
@ -2432,6 +2576,150 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
|||
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
|
||||
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
|
||||
{ ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
|
||||
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
|
||||
|
||||
/* Predicates. */
|
||||
{ ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
|
||||
|
|
|
|||
|
|
@ -905,7 +905,6 @@ static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
|
|||
static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
|
||||
static rtx altivec_expand_predicate_builtin (enum insn_code,
|
||||
const char *, tree, rtx);
|
||||
static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
|
||||
static rtx altivec_expand_stv_builtin (enum insn_code, tree);
|
||||
static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
|
||||
static rtx altivec_expand_vec_set_builtin (tree);
|
||||
|
|
@ -8065,7 +8064,7 @@ paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
|
|||
}
|
||||
|
||||
static rtx
|
||||
altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
|
||||
altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
|
||||
{
|
||||
rtx pat, addr;
|
||||
tree arg0 = CALL_EXPR_ARG (exp, 0);
|
||||
|
|
@ -8093,12 +8092,12 @@ altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
|
|||
|
||||
if (op0 == const0_rtx)
|
||||
{
|
||||
addr = gen_rtx_MEM (tmode, op1);
|
||||
addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
|
||||
}
|
||||
else
|
||||
{
|
||||
op0 = copy_to_mode_reg (mode0, op0);
|
||||
addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
|
||||
addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
|
||||
}
|
||||
|
||||
pat = GEN_FCN (icode) (target, addr);
|
||||
|
|
@ -8605,6 +8604,15 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
|
|||
case ALTIVEC_BUILTIN_STVXL:
|
||||
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
|
||||
|
||||
case ALTIVEC_BUILTIN_STVLX:
|
||||
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
|
||||
case ALTIVEC_BUILTIN_STVLXL:
|
||||
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
|
||||
case ALTIVEC_BUILTIN_STVRX:
|
||||
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
|
||||
case ALTIVEC_BUILTIN_STVRXL:
|
||||
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
|
||||
|
||||
case ALTIVEC_BUILTIN_MFVSCR:
|
||||
icode = CODE_FOR_altivec_mfvscr;
|
||||
tmode = insn_data[icode].operand[0].mode;
|
||||
|
|
@ -8707,25 +8715,37 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
|
|||
{
|
||||
case ALTIVEC_BUILTIN_LVSL:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
|
||||
exp, target);
|
||||
exp, target, false);
|
||||
case ALTIVEC_BUILTIN_LVSR:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
|
||||
exp, target);
|
||||
exp, target, false);
|
||||
case ALTIVEC_BUILTIN_LVEBX:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
|
||||
exp, target);
|
||||
exp, target, false);
|
||||
case ALTIVEC_BUILTIN_LVEHX:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
|
||||
exp, target);
|
||||
exp, target, false);
|
||||
case ALTIVEC_BUILTIN_LVEWX:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
|
||||
exp, target);
|
||||
exp, target, false);
|
||||
case ALTIVEC_BUILTIN_LVXL:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
|
||||
exp, target);
|
||||
exp, target, false);
|
||||
case ALTIVEC_BUILTIN_LVX:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
|
||||
exp, target);
|
||||
exp, target, false);
|
||||
case ALTIVEC_BUILTIN_LVLX:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
|
||||
exp, target, true);
|
||||
case ALTIVEC_BUILTIN_LVLXL:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
|
||||
exp, target, true);
|
||||
case ALTIVEC_BUILTIN_LVRX:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
|
||||
exp, target, true);
|
||||
case ALTIVEC_BUILTIN_LVRXL:
|
||||
return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
|
||||
exp, target, true);
|
||||
default:
|
||||
break;
|
||||
/* Fall through. */
|
||||
|
|
@ -9910,6 +9930,28 @@ altivec_init_builtins (void)
|
|||
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
|
||||
|
||||
if (rs6000_cpu == PROCESSOR_CELL)
|
||||
{
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
|
||||
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
|
||||
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
|
||||
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
|
||||
}
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
|
||||
|
||||
def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
|
||||
|
|
|
|||
|
|
@ -2543,10 +2543,18 @@ enum rs6000_builtins
|
|||
ALTIVEC_BUILTIN_LVXL,
|
||||
ALTIVEC_BUILTIN_LVX,
|
||||
ALTIVEC_BUILTIN_STVX,
|
||||
ALTIVEC_BUILTIN_LVLX,
|
||||
ALTIVEC_BUILTIN_LVLXL,
|
||||
ALTIVEC_BUILTIN_LVRX,
|
||||
ALTIVEC_BUILTIN_LVRXL,
|
||||
ALTIVEC_BUILTIN_STVEBX,
|
||||
ALTIVEC_BUILTIN_STVEHX,
|
||||
ALTIVEC_BUILTIN_STVEWX,
|
||||
ALTIVEC_BUILTIN_STVXL,
|
||||
ALTIVEC_BUILTIN_STVLX,
|
||||
ALTIVEC_BUILTIN_STVLXL,
|
||||
ALTIVEC_BUILTIN_STVRX,
|
||||
ALTIVEC_BUILTIN_STVRXL,
|
||||
ALTIVEC_BUILTIN_VCMPBFP_P,
|
||||
ALTIVEC_BUILTIN_VCMPEQFP_P,
|
||||
ALTIVEC_BUILTIN_VCMPEQUB_P,
|
||||
|
|
@ -2621,6 +2629,10 @@ enum rs6000_builtins
|
|||
ALTIVEC_BUILTIN_VEC_LVEBX,
|
||||
ALTIVEC_BUILTIN_VEC_LVEHX,
|
||||
ALTIVEC_BUILTIN_VEC_LVEWX,
|
||||
ALTIVEC_BUILTIN_VEC_LVLX,
|
||||
ALTIVEC_BUILTIN_VEC_LVLXL,
|
||||
ALTIVEC_BUILTIN_VEC_LVRX,
|
||||
ALTIVEC_BUILTIN_VEC_LVRXL,
|
||||
ALTIVEC_BUILTIN_VEC_LVSL,
|
||||
ALTIVEC_BUILTIN_VEC_LVSR,
|
||||
ALTIVEC_BUILTIN_VEC_MADD,
|
||||
|
|
@ -2680,6 +2692,10 @@ enum rs6000_builtins
|
|||
ALTIVEC_BUILTIN_VEC_STVEBX,
|
||||
ALTIVEC_BUILTIN_VEC_STVEHX,
|
||||
ALTIVEC_BUILTIN_VEC_STVEWX,
|
||||
ALTIVEC_BUILTIN_VEC_STVLX,
|
||||
ALTIVEC_BUILTIN_VEC_STVLXL,
|
||||
ALTIVEC_BUILTIN_VEC_STVRX,
|
||||
ALTIVEC_BUILTIN_VEC_STVRXL,
|
||||
ALTIVEC_BUILTIN_VEC_SUB,
|
||||
ALTIVEC_BUILTIN_VEC_SUBC,
|
||||
ALTIVEC_BUILTIN_VEC_SUBS,
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
2008-10-01 Andrew Pinski <andrew_pinski@playstation.sony.com>
|
||||
|
||||
* gcc.target/powerpc/altivec_check.h (altivec_cell_check): New function.
|
||||
* gcc.target/powerpc/altivec-cell-6.c: New test.
|
||||
* gcc.target/powerpc/altivec-cell-7.c: New test.
|
||||
* gcc.target/powerpc/altivec-cell-8.c: New test.
|
||||
|
||||
2008-10-01 Richard Guenther <rguenther@suse.de>
|
||||
|
||||
PR tree-optimization/37617
|
||||
|
|
@ -5,8 +12,8 @@
|
|||
|
||||
2008-10-01 Richard Guenther <rguenther@suse.de>
|
||||
|
||||
PR middle-end/37285
|
||||
* gcc.c-torture/compile/pr37285.c: New testcase.
|
||||
PR middle-end/37285
|
||||
* gcc.c-torture/compile/pr37285.c: New testcase.
|
||||
|
||||
2008-10-01 Kai Tietz <kai.tietz@onevision.com>
|
||||
|
||||
|
|
|
|||
12
gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c
Normal file
12
gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_altivec_ok } */
|
||||
/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
|
||||
#include <altivec.h>
|
||||
|
||||
/* This used to ICE with reloading of a constant address. */
|
||||
|
||||
vector float f(void)
|
||||
{
|
||||
vector float * a = (void*)16;
|
||||
return vec_lvlx (0, a);
|
||||
}
|
||||
28
gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c
Normal file
28
gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_altivec_ok } */
|
||||
/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
|
||||
/* { dg-final { scan-assembler-times "vor" 2 } } */
|
||||
#include <altivec.h>
|
||||
|
||||
/* Make sure that lvlx and lvrx are not combined into one insn and
|
||||
we still get a vor. */
|
||||
|
||||
vector unsigned char
|
||||
lvx_float (long off, float *p)
|
||||
{
|
||||
vector unsigned char l, r;
|
||||
|
||||
l = (vector unsigned char) vec_lvlx (off, p);
|
||||
r = (vector unsigned char) vec_lvrx (off, p);
|
||||
return vec_or(l, r);
|
||||
}
|
||||
|
||||
vector unsigned char
|
||||
lvxl_float (long off, float *p)
|
||||
{
|
||||
vector unsigned char l, r;
|
||||
|
||||
l = (vector unsigned char) vec_lvlxl (off, p);
|
||||
r = (vector unsigned char) vec_lvrxl (off, p);
|
||||
return vec_or(l, r);
|
||||
}
|
||||
56
gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c
Normal file
56
gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target powerpc_altivec_ok } */
|
||||
/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
|
||||
#include <altivec.h>
|
||||
#include <string.h>
|
||||
#include "altivec_check.h"
|
||||
|
||||
typedef short int sint16;
|
||||
typedef signed char int8;
|
||||
|
||||
int main1(void) __attribute__((noinline));
|
||||
int main1(void)
|
||||
{
|
||||
sint16 test_vector[4] = { 1678, -2356, 19246, -17892 };
|
||||
int8 test_dst[128] __attribute__(( aligned( 16 )));
|
||||
float test_out[4] __attribute__(( aligned( 16 )));
|
||||
int p;
|
||||
|
||||
for( p = 0; p < 24; ++p )
|
||||
{
|
||||
memset( test_dst, 0, 128 );
|
||||
memcpy( &test_dst[p], test_vector, 8 );
|
||||
{
|
||||
vector float VR, VL, V;
|
||||
/* load the righthand section of the misaligned vector */
|
||||
VR = (vector float) vec_lvrx( 8, &test_dst[p] );
|
||||
VL = (vector float) vec_lvlx( 0, &test_dst[p] );
|
||||
/* Vector Shift Left Double by Octet Immediate, move the right hand section into the bytes */
|
||||
VR = vec_vsldoi( VR, VR, 2 << 2 );
|
||||
/* or those two together */
|
||||
V = vec_vor( VL, VR );
|
||||
/* sign extend */
|
||||
V = (vector float) vec_vupkhsh((vector bool short)V );
|
||||
/* fixed to float by S16_SHIFT_BITS bits */
|
||||
V = (vector float) vec_vcfsx ((vector signed int)V, 5 );
|
||||
|
||||
vec_stvx( V, 0, &test_out[0] );
|
||||
if (test_out[0] != 52.437500)
|
||||
abort ();
|
||||
if (test_out[1] != -73.625000)
|
||||
abort ();
|
||||
if (test_out[2] != 601.437500)
|
||||
abort ();
|
||||
if (test_out[3] != -559.125000)
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
altivec_cell_check ();
|
||||
return main1();
|
||||
}
|
||||
|
|
@ -22,3 +22,17 @@ void altivec_check(void) {
|
|||
#endif
|
||||
signal (SIGILL, SIG_DFL);
|
||||
}
|
||||
|
||||
void altivec_cell_check (void)
|
||||
{
|
||||
/* Exit on systems without the Cell Altivec instructions. */
|
||||
signal (SIGILL, sig_ill_handler);
|
||||
#ifdef __MACH__
|
||||
asm volatile ("vor v0,v0,v0");
|
||||
asm volatile ("lvlx v0,r0,r0");
|
||||
#else
|
||||
asm volatile ("vor 0,0,0");
|
||||
asm volatile ("lvlx 0,0,0");
|
||||
#endif
|
||||
signal (SIGILL, SIG_DFL);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue