revert: rtl.h (struct rtx_def): ...
2013-04-24 Vladimir Makarov <vmakarov@redhat.com> Revert: 2013-04-24 Vladimir Makarov <vmakarov@redhat.com> * rtl.h (struct rtx_def): ... From-SVN: r198266
This commit is contained in:
Vladimir Makarov
Vladimir Makarov
parent
ec98d01014
commit
0ae24cc897
7 changed files with 72 additions and 167 deletions
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@ -1,3 +1,9 @@
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2013-04-24 Vladimir Makarov <vmakarov@redhat.com>
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Revert:
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2013-04-24 Vladimir Makarov <vmakarov@redhat.com>
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* rtl.h (struct rtx_def): ...
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2013-04-24 Vladimir Makarov <vmakarov@redhat.com>
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PR rtl-optimizations/57046
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@ -135,11 +135,10 @@
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reload insns. */
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static int bb_reload_num;
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/* The current insn being processed and corresponding its single set
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(NULL otherwise), its data (basic block, the insn data, the insn
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static data, and the mode of each operand). */
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/* The current insn being processed and corresponding its data (basic
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block, the insn data, the insn static data, and the mode of each
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operand). */
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static rtx curr_insn;
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static rtx curr_insn_set;
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static basic_block curr_bb;
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static lra_insn_recog_data_t curr_id;
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static struct lra_static_insn_data *curr_static_id;
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@ -699,7 +698,6 @@ match_reload (signed char out, signed char *ins, enum reg_class goal_class,
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new_out_reg = gen_lowpart_SUBREG (outmode, reg);
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else
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new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
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LRA_SUBREG_P (new_out_reg) = 1;
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/* If the input reg is dying here, we can use the same hard
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register for REG and IN_RTX. We do it only for original
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pseudos as reload pseudos can die although original
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@ -723,7 +721,6 @@ match_reload (signed char out, signed char *ins, enum reg_class goal_class,
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it at the end of LRA work. */
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clobber = emit_clobber (new_out_reg);
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LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
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LRA_SUBREG_P (new_in_reg) = 1;
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if (GET_CODE (in_rtx) == SUBREG)
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{
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rtx subreg_reg = SUBREG_REG (in_rtx);
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@ -858,34 +855,40 @@ static rtx
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emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
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{
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if (GET_MODE (mem_pseudo) != GET_MODE (val))
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{
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val = gen_rtx_SUBREG (GET_MODE (mem_pseudo),
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GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val,
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0);
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LRA_SUBREG_P (val) = 1;
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}
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val = gen_rtx_SUBREG (GET_MODE (mem_pseudo),
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GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val,
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0);
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return (to_p
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? gen_move_insn (mem_pseudo, val)
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: gen_move_insn (val, mem_pseudo));
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? gen_move_insn (mem_pseudo, val)
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: gen_move_insn (val, mem_pseudo));
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}
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/* Process a special case insn (register move), return true if we
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don't need to process it anymore. INSN should be a single set
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insn. Set up that RTL was changed through CHANGE_P and macro
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SECONDARY_MEMORY_NEEDED says to use secondary memory through
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SEC_MEM_P. */
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don't need to process it anymore. Return that RTL was changed
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through CHANGE_P and macro SECONDARY_MEMORY_NEEDED says to use
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secondary memory through SEC_MEM_P. */
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static bool
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check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
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check_and_process_move (bool *change_p, bool *sec_mem_p)
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{
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int sregno, dregno;
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rtx dest, src, dreg, sreg, old_sreg, new_reg, before, scratch_reg;
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rtx set, dest, src, dreg, sreg, old_sreg, new_reg, before, scratch_reg;
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enum reg_class dclass, sclass, secondary_class;
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enum machine_mode sreg_mode;
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secondary_reload_info sri;
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lra_assert (curr_insn_set != NULL_RTX);
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dreg = dest = SET_DEST (curr_insn_set);
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sreg = src = SET_SRC (curr_insn_set);
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*sec_mem_p = *change_p = false;
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if ((set = single_set (curr_insn)) == NULL)
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return false;
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dreg = dest = SET_DEST (set);
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sreg = src = SET_SRC (set);
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/* Quick check on the right move insn which does not need
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reloads. */
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if ((dclass = get_op_class (dest)) != NO_REGS
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&& (sclass = get_op_class (src)) != NO_REGS
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/* The backend guarantees that register moves of cost 2 never
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need reloads. */
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&& targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2)
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return true;
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if (GET_CODE (dest) == SUBREG)
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dreg = SUBREG_REG (dest);
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if (GET_CODE (src) == SUBREG)
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@ -893,6 +896,7 @@ check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
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if (! REG_P (dreg) || ! REG_P (sreg))
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return false;
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sclass = dclass = NO_REGS;
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dreg = get_equiv_substitution (dreg);
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if (REG_P (dreg))
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dclass = get_reg_class (REGNO (dreg));
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if (dclass == ALL_REGS)
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@ -906,6 +910,7 @@ check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
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return false;
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sreg_mode = GET_MODE (sreg);
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old_sreg = sreg;
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sreg = get_equiv_substitution (sreg);
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if (REG_P (sreg))
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sclass = get_reg_class (REGNO (sreg));
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if (sclass == ALL_REGS)
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@ -1002,7 +1007,7 @@ check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
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if (GET_CODE (src) == SUBREG)
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SUBREG_REG (src) = new_reg;
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else
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SET_SRC (curr_insn_set) = new_reg;
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SET_SRC (set) = new_reg;
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}
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else
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{
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@ -1199,10 +1204,7 @@ simplify_operand_subreg (int nop, enum machine_mode reg_mode)
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&& (hard_regno_nregs[hard_regno][GET_MODE (reg)]
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>= hard_regno_nregs[hard_regno][mode])
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&& simplify_subreg_regno (hard_regno, GET_MODE (reg),
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SUBREG_BYTE (operand), mode) < 0
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/* Don't reload subreg for matching reload. It is actually
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valid subreg in LRA. */
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&& ! LRA_SUBREG_P (operand))
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SUBREG_BYTE (operand), mode) < 0)
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|| CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
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{
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enum op_type type = curr_static_id->operand[nop].type;
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@ -1309,14 +1311,6 @@ general_constant_p (rtx x)
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return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
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}
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static bool
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reg_in_class_p (rtx reg, enum reg_class cl)
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{
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if (cl == NO_REGS)
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return get_reg_class (REGNO (reg)) == NO_REGS;
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return in_class_p (reg, cl, NULL);
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}
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/* Major function to choose the current insn alternative and what
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operands should be reloaded and how. If ONLY_ALTERNATIVE is not
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negative we should consider only this alternative. Return false if
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@ -1396,7 +1390,7 @@ process_alt_operands (int only_alternative)
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for (nalt = 0; nalt < n_alternatives; nalt++)
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{
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/* Loop over operands for one constraint alternative. */
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#if HAVE_ATTR_enabled
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#ifdef HAVE_ATTR_enabled
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if (curr_id->alternative_enabled_p != NULL
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&& ! curr_id->alternative_enabled_p[nalt])
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continue;
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@ -2060,31 +2054,6 @@ process_alt_operands (int only_alternative)
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if (early_clobber_p && operand_reg[nop] != NULL_RTX)
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early_clobbered_nops[early_clobbered_regs_num++] = nop;
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}
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if (curr_insn_set != NULL_RTX && n_operands == 2
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&& ((! curr_alt_win[0] && ! curr_alt_win[1]
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&& REG_P (no_subreg_reg_operand[0])
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&& REG_P (no_subreg_reg_operand[1])
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&& (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
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|| reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
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|| (! curr_alt_win[0] && curr_alt_win[1]
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&& REG_P (no_subreg_reg_operand[1])
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&& reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
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|| (curr_alt_win[0] && ! curr_alt_win[1]
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&& REG_P (no_subreg_reg_operand[0])
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&& reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
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&& (! CONST_POOL_OK_P (curr_operand_mode[1],
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no_subreg_reg_operand[1])
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|| (targetm.preferred_reload_class
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(no_subreg_reg_operand[1],
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(enum reg_class) curr_alt[1]) != NO_REGS))
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/* If it is a result of recent elimination in move
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insn we can transform it into an add still by
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using this alternative. */
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&& GET_CODE (no_subreg_reg_operand[1]) != PLUS)))
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/* We have a move insn and a new reload insn will be similar
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to the current insn. We should avoid such situation as it
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results in LRA cycling. */
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overall += LRA_MAX_REJECT;
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ok_p = true;
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curr_alt_dont_inherit_ops_num = 0;
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for (nop = 0; nop < early_clobbered_regs_num; nop++)
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@ -2456,35 +2425,27 @@ process_address (int nop, rtx *before, rtx *after)
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&& process_addr_reg (ad.index_term, before, NULL, INDEX_REG_CLASS))
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change_p = true;
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#ifdef EXTRA_CONSTRAINT_STR
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/* Target hooks sometimes reject extra constraint addresses -- use
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EXTRA_CONSTRAINT_STR for the validation. */
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if (constraint[0] != 'p'
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&& EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint)
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&& EXTRA_CONSTRAINT_STR (op, constraint[0], constraint))
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return change_p;
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#endif
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/* There are three cases where the shape of *AD.INNER may now be invalid:
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1) the original address was valid, but either elimination or
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equiv_address_substitution was applied and that made
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the address invalid.
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equiv_address_substitution applied a displacement that made
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it invalid.
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2) the address is an invalid symbolic address created by
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force_const_to_mem.
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3) the address is a frame address with an invalid offset.
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All these cases involve a non-autoinc address, so there is no
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point revalidating other types. */
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if (ad.autoinc_p || valid_address_p (&ad))
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All these cases involve a displacement and a non-autoinc address,
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so there is no point revalidating other types. */
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if (ad.disp == NULL || ad.autoinc_p || valid_address_p (&ad))
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return change_p;
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/* Any index existed before LRA started, so we can assume that the
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presence and shape of the index is valid. */
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push_to_sequence (*before);
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lra_assert (ad.disp == ad.disp_term);
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gcc_assert (ad.segment == NULL);
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gcc_assert (ad.disp == ad.disp_term);
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if (ad.base == NULL)
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{
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if (ad.index == NULL)
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@ -2492,39 +2453,26 @@ process_address (int nop, rtx *before, rtx *after)
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int code = -1;
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enum reg_class cl = base_reg_class (ad.mode, ad.as,
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SCRATCH, SCRATCH);
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rtx addr = *ad.inner;
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rtx disp = *ad.disp;
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new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
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new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
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#ifdef HAVE_lo_sum
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{
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rtx insn;
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rtx last = get_last_insn ();
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/* addr => lo_sum (new_base, addr), case (2) above. */
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/* disp => lo_sum (new_base, disp), case (2) above. */
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insn = emit_insn (gen_rtx_SET
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(VOIDmode, new_reg,
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gen_rtx_HIGH (Pmode, copy_rtx (addr))));
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gen_rtx_HIGH (Pmode, copy_rtx (disp))));
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code = recog_memoized (insn);
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if (code >= 0)
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{
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*ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
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*ad.disp = gen_rtx_LO_SUM (Pmode, new_reg, disp);
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if (! valid_address_p (ad.mode, *ad.outer, ad.as))
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{
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/* Try to put lo_sum into register. */
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insn = emit_insn (gen_rtx_SET
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(VOIDmode, new_reg,
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gen_rtx_LO_SUM (Pmode, new_reg, addr)));
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code = recog_memoized (insn);
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if (code >= 0)
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{
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*ad.inner = new_reg;
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if (! valid_address_p (ad.mode, *ad.outer, ad.as))
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{
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*ad.inner = addr;
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code = -1;
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}
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}
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*ad.disp = disp;
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code = -1;
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}
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}
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if (code < 0)
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@ -2533,9 +2481,9 @@ process_address (int nop, rtx *before, rtx *after)
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#endif
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if (code < 0)
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{
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/* addr => new_base, case (2) above. */
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lra_emit_move (new_reg, addr);
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*ad.inner = new_reg;
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/* disp => new_base, case (2) above. */
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lra_emit_move (new_reg, disp);
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*ad.disp = new_reg;
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}
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}
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else
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@ -2702,24 +2650,6 @@ emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount)
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return result;
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}
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/* Return true if the current move insn does not need processing as we
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already know that it satisfies its constraints. */
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static bool
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simple_move_p (void)
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{
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rtx dest, src;
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enum reg_class dclass, sclass;
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lra_assert (curr_insn_set != NULL_RTX);
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dest = SET_DEST (curr_insn_set);
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src = SET_SRC (curr_insn_set);
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return ((dclass = get_op_class (dest)) != NO_REGS
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&& (sclass = get_op_class (src)) != NO_REGS
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/* The backend guarantees that register moves of cost 2
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never need reloads. */
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&& targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2);
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}
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/* Swap operands NOP and NOP + 1. */
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static inline void
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swap_operands (int nop)
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@ -2763,13 +2693,12 @@ curr_insn_transform (void)
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int max_regno_before;
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int reused_alternative_num;
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curr_insn_set = single_set (curr_insn);
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if (curr_insn_set != NULL_RTX && simple_move_p ())
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return false;
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no_input_reloads_p = no_output_reloads_p = false;
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goal_alt_number = -1;
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change_p = sec_mem_p = false;
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if (check_and_process_move (&change_p, &sec_mem_p))
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return change_p;
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/* JUMP_INSNs and CALL_INSNs are not allowed to have any output
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reloads; neither are insns that SET cc0. Insns that use CC0 are
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not allowed to have any input reloads. */
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@ -2864,10 +2793,6 @@ curr_insn_transform (void)
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we chose previously may no longer be valid. */
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lra_set_used_insn_alternative (curr_insn, -1);
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if (curr_insn_set != NULL_RTX
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&& check_and_process_move (&change_p, &sec_mem_p))
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return change_p;
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try_swapped:
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reused_alternative_num = curr_id->used_insn_alternative;
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@ -4896,7 +4821,7 @@ inherit_in_ebb (rtx head, rtx tail)
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/* This value affects EBB forming. If probability of edge from EBB to
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a BB is not greater than the following value, we don't add the BB
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to EBB. */
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#define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
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#define EBB_PROBABILITY_CUTOFF (REG_BR_PROB_BASE / 2)
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/* Current number of inheritance/split iteration. */
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int lra_inheritance_iter;
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@ -977,9 +977,6 @@ eliminate_regs_in_insn (rtx insn, bool replace_p)
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}
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}
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if (! validate_p)
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return;
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/* Substitute the operands; the new values are in the substed_operand
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array. */
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for (i = 0; i < static_id->n_operands; i++)
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@ -987,13 +984,16 @@ eliminate_regs_in_insn (rtx insn, bool replace_p)
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for (i = 0; i < static_id->n_dups; i++)
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*id->dup_loc[i] = substed_operand[(int) static_id->dup_num[i]];
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/* If we had a move insn but now we don't, re-recognize it.
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This will cause spurious re-recognition if the old move had a
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PARALLEL since the new one still will, but we can't call
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single_set without having put new body into the insn and the
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re-recognition won't hurt in this rare case. */
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id = lra_update_insn_recog_data (insn);
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static_id = id->insn_static_data;
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if (validate_p)
|
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{
|
||||
/* If we had a move insn but now we don't, re-recognize it.
|
||||
This will cause spurious re-recognition if the old move had a
|
||||
PARALLEL since the new one still will, but we can't call
|
||||
single_set without having put new body into the insn and the
|
||||
re-recognition won't hurt in this rare case. */
|
||||
id = lra_update_insn_recog_data (insn);
|
||||
static_id = id->insn_static_data;
|
||||
}
|
||||
}
|
||||
|
||||
/* Spill pseudos which are assigned to hard registers in SET. Add
|
||||
|
|
|
|||
|
|
@ -548,11 +548,6 @@ lra_spill (void)
|
|||
for (i = 0; i < n; i++)
|
||||
if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX)
|
||||
assign_mem_slot (pseudo_regnos[i]);
|
||||
if (n > 0 && crtl->stack_alignment_needed)
|
||||
/* If we have a stack frame, we must align it now. The stack size
|
||||
may be a part of the offset computation for register
|
||||
elimination. */
|
||||
assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
|
||||
if (lra_dump_file != NULL)
|
||||
{
|
||||
for (i = 0; i < slots_num; i++)
|
||||
|
|
@ -649,12 +644,10 @@ lra_final_code_change (void)
|
|||
}
|
||||
|
||||
lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
|
||||
struct lra_static_insn_data *static_id = id->insn_static_data;
|
||||
bool insn_change_p = false;
|
||||
|
||||
for (i = id->insn_static_data->n_operands - 1; i >= 0; i--)
|
||||
if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator)
|
||||
&& alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
|
||||
if (alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
|
||||
{
|
||||
lra_update_dup (id, i);
|
||||
insn_change_p = true;
|
||||
|
|
|
|||
|
|
@ -2203,10 +2203,6 @@ lra (FILE *f)
|
|||
|
||||
timevar_push (TV_LRA);
|
||||
|
||||
/* Make sure that the last insn is a note. Some subsequent passes
|
||||
need it. */
|
||||
emit_note (NOTE_INSN_DELETED);
|
||||
|
||||
COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs);
|
||||
|
||||
init_reg_info ();
|
||||
|
|
@ -2263,11 +2259,6 @@ lra (FILE *f)
|
|||
bitmap_initialize (&lra_split_regs, ®_obstack);
|
||||
bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack);
|
||||
live_p = false;
|
||||
if (get_frame_size () != 0 && crtl->stack_alignment_needed)
|
||||
/* If we have a stack frame, we must align it now. The stack size
|
||||
may be a part of the offset computation for register
|
||||
elimination. */
|
||||
assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
|
||||
for (;;)
|
||||
{
|
||||
for (;;)
|
||||
|
|
|
|||
|
|
@ -1065,11 +1065,7 @@ register_operand (rtx op, enum machine_mode mode)
|
|||
&& REGNO (sub) < FIRST_PSEUDO_REGISTER
|
||||
&& REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
|
||||
&& GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
|
||||
&& GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
|
||||
/* LRA can generate some invalid SUBREGS just for matched
|
||||
operand reload presentation. LRA needs to treat them as
|
||||
valid. */
|
||||
&& ! LRA_SUBREG_P (op))
|
||||
&& GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT)
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -265,8 +265,7 @@ struct GTY((chain_next ("RTX_NEXT (&%h)"),
|
|||
1 in a SET that is for a return.
|
||||
In a CODE_LABEL, part of the two-bit alternate entry field.
|
||||
1 in a CONCAT is VAL_EXPR_IS_COPIED in var-tracking.c.
|
||||
1 in a VALUE is SP_BASED_VALUE_P in cselib.c.
|
||||
1 in a SUBREG generated by LRA for reload insns. */
|
||||
1 in a VALUE is SP_BASED_VALUE_P in cselib.c. */
|
||||
unsigned int jump : 1;
|
||||
/* In a CODE_LABEL, part of the two-bit alternate entry field.
|
||||
1 in a MEM if it cannot trap.
|
||||
|
|
@ -1412,11 +1411,6 @@ do { \
|
|||
((RTL_FLAG_CHECK1("SUBREG_PROMOTED_UNSIGNED_P", (RTX), SUBREG)->volatil) \
|
||||
? -1 : (int) (RTX)->unchanging)
|
||||
|
||||
/* True if the subreg was generated by LRA for reload insns. Such
|
||||
subregs are valid only during LRA. */
|
||||
#define LRA_SUBREG_P(RTX) \
|
||||
(RTL_FLAG_CHECK1("LRA_SUBREG_P", (RTX), SUBREG)->jump)
|
||||
|
||||
/* Access various components of an ASM_OPERANDS rtx. */
|
||||
|
||||
#define ASM_OPERANDS_TEMPLATE(RTX) XCSTR (RTX, 0, ASM_OPERANDS)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue