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RISC-V: Fix regression

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Due to recent middle-end loop vectorizer changes, these tests have regression and
the changes are reasonable. Adapt test to fix the regression.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/shift-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto.
This commit is contained in:
Juzhe-Zhong 2024-01-30 09:19:06 +08:00 • committed by Pan Li
parent f07068197d
commit 0ac37563fa
5 changed files with 5 additions and 5 deletions
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2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
View file

@ -4,5 +4,5 @@
#include "shift-template.h"
/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */
/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
View file

@ -4,5 +4,5 @@
#include "shift-template.h"
/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */
/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
View file

@ -53,5 +53,5 @@ DEF_OP_VV (mod, 128, int64_t, %)
DEF_OP_VV (mod, 256, int64_t, %)
DEF_OP_VV (mod, 512, int64_t, %)
/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 47 } } */
/* { dg-final { scan-assembler-not {csrr} } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
View file

@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, >>)
DEF_OP_VV (shift, 256, int64_t, >>)
DEF_OP_VV (shift, 512, int64_t, >>)
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 35 } } */
/* { dg-final { scan-assembler-not {csrr} } } */

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
View file

@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, uint64_t, >>)
DEF_OP_VV (shift, 256, uint64_t, >>)
DEF_OP_VV (shift, 512, uint64_t, >>)
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
/* { dg-final { scan-assembler-not {csrr} } } */