AArch64: Add UNSPECV_PATCHABLE_AREA [PR98776]
Currently patchable area is at the wrong place on AArch64. It is placed immediately after function label, before .cfi_startproc. This patch adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and modifies aarch64_print_patchable_function_entry to avoid placing patchable area before .cfi_startproc. gcc/ PR target/98776 * config/aarch64/aarch64-protos.h (aarch64_output_patchable_area): Declared. * config/aarch64/aarch64.cc (aarch64_print_patchable_function_entry): Emit an UNSPECV_PATCHABLE_AREA pseudo instruction. (aarch64_output_patchable_area): New. * config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New. (patchable_area): Define. gcc/testsuite/ PR target/98776 * gcc.target/aarch64/pr98776.c: New. * gcc.target/aarch64/pr92424-2.c: Adjust pattern. * gcc.target/aarch64/pr92424-3.c: Adjust pattern.
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Sebastian Pop
parent
955093369e
commit
09c91caeb8
6 changed files with 70 additions and 17 deletions
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@ -1075,4 +1075,6 @@ const char *aarch64_indirect_call_asm (rtx);
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extern bool aarch64_harden_sls_retbr_p (void);
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extern bool aarch64_harden_sls_blr_p (void);
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extern void aarch64_output_patchable_area (unsigned int, bool);
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#endif /* GCC_AARCH64_PROTOS_H */
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@ -22672,30 +22672,56 @@ aarch64_declare_function_name (FILE *stream, const char* name,
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cfun->machine->label_is_assembled = true;
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}
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/* Implement PRINT_PATCHABLE_FUNCTION_ENTRY. Check if the patch area is after
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the function label and emit a BTI if necessary. */
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/* Implement PRINT_PATCHABLE_FUNCTION_ENTRY. */
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void
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aarch64_print_patchable_function_entry (FILE *file,
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unsigned HOST_WIDE_INT patch_area_size,
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bool record_p)
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{
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if (cfun->machine->label_is_assembled
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&& aarch64_bti_enabled ()
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&& !cgraph_node::get (cfun->decl)->only_called_directly_p ())
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if (!cfun->machine->label_is_assembled)
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{
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/* Remove the BTI that follows the patch area and insert a new BTI
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before the patch area right after the function label. */
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rtx_insn *insn = next_real_nondebug_insn (get_insns ());
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if (insn
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&& INSN_P (insn)
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&& GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
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&& XINT (PATTERN (insn), 1) == UNSPECV_BTI_C)
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delete_insn (insn);
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asm_fprintf (file, "\thint\t34 // bti c\n");
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/* Emit the patching area before the entry label, if any. */
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default_print_patchable_function_entry (file, patch_area_size,
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record_p);
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return;
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}
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default_print_patchable_function_entry (file, patch_area_size, record_p);
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rtx pa = gen_patchable_area (GEN_INT (patch_area_size),
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GEN_INT (record_p));
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basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
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if (!aarch64_bti_enabled ()
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|| cgraph_node::get (cfun->decl)->only_called_directly_p ())
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{
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/* Emit the patchable_area at the beginning of the function. */
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rtx_insn *insn = emit_insn_before (pa, BB_HEAD (bb));
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INSN_ADDRESSES_NEW (insn, -1);
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return;
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}
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rtx_insn *insn = next_real_nondebug_insn (get_insns ());
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if (!insn
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|| !INSN_P (insn)
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|| GET_CODE (PATTERN (insn)) != UNSPEC_VOLATILE
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|| XINT (PATTERN (insn), 1) != UNSPECV_BTI_C)
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{
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/* Emit a BTI_C. */
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insn = emit_insn_before (gen_bti_c (), BB_HEAD (bb));
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}
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/* Emit the patchable_area after BTI_C. */
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insn = emit_insn_after (pa, insn);
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INSN_ADDRESSES_NEW (insn, -1);
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}
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/* Output patchable area. */
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void
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aarch64_output_patchable_area (unsigned int patch_area_size, bool record_p)
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{
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default_print_patchable_function_entry (asm_out_file, patch_area_size,
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record_p);
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}
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/* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */
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@ -303,6 +303,7 @@
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UNSPEC_TAG_SPACE ; Translate address to MTE tag address space.
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UNSPEC_LD1RO
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UNSPEC_SALT_ADDR
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UNSPECV_PATCHABLE_AREA
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])
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(define_c_enum "unspecv" [
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@ -7825,6 +7826,19 @@
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[(set_attr "type" "ls64")]
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)
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(define_insn "patchable_area"
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[(unspec_volatile [(match_operand 0 "const_int_operand")
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(match_operand 1 "const_int_operand")]
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UNSPECV_PATCHABLE_AREA)]
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""
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{
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aarch64_output_patchable_area (INTVAL (operands[0]),
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INTVAL (operands[1]) != 0);
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return "";
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}
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[(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]
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)
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;; AdvSIMD Stuff
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(include "aarch64-simd.md")
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@ -9,4 +9,4 @@ __attribute__ ((target("branch-protection=bti"),
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f10_bti ()
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{
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}
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/* { dg-final { scan-assembler "f10_bti:\n\thint\t34 // bti c\n.*\.LPFE0:\n\tnop\n.*\tret\n" } } */
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/* { dg-final { scan-assembler "hint\t34 // bti c\n.*\.LPFE0:\n\tnop\n.*\tret\n" } } */
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@ -9,4 +9,4 @@ __attribute__ ((target("branch-protection=bti+pac-ret+leaf"),
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f10_pac ()
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{
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}
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/* { dg-final { scan-assembler "f10_pac:\n\thint\t34 // bti c\n.*\.LPFE0:\n\tnop\n.*\thint\t25 // paciasp\n.*\thint\t29 // autiasp\n.*\tret\n" } } */
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/* { dg-final { scan-assembler "hint\t34 // bti c\n.*\.LPFE0:\n\tnop\n.*\thint\t25 // paciasp\n.*\thint\t29 // autiasp\n.*\tret\n" } } */
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11
gcc/testsuite/gcc.target/aarch64/pr98776.c
Normal file
11
gcc/testsuite/gcc.target/aarch64/pr98776.c
Normal file
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@ -0,0 +1,11 @@
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/* { dg-do "compile" } */
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/* { dg-options "-O1 -fpatchable-function-entry=1 -fasynchronous-unwind-tables" } */
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/* Test the placement of the .LPFE0 label. */
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void
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foo (void)
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{
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}
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/* { dg-final { scan-assembler "\t\.cfi_startproc\n.*\.LPFE0:\n\tnop\n\tret\n" } } */
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