From 09a08df71939cc0035ebae85220ff0214a38fb7c Mon Sep 17 00:00:00 2001
From: Victor Do Nascimento <victor.donascimento@arm.com>
Date: Sun, 29 Oct 2023 01:49:45 +0100
Subject: [PATCH] aarch64: Add rsr128 and wsr128 ACLE tests

Extend existing unit tests for the ACLE system register manipulation
functions to include 128-bit tests.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/rwsr.c (get_rsr128): New.
	(set_wsr128): Likewise.
---
 gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 32 ++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
index 93c48c4caf0..6feb0bef2d6 100644
--- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
+++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
@@ -6,6 +6,38 @@
 
 #include <arm_acle.h>
 
+#pragma GCC push_options
+#pragma GCC target ("arch=armv9.4-a+d128")
+
+#ifndef __ARM_FEATURE_SYSREG128
+#error "__ARM_FEATURE_SYSREG128 feature macro not defined."
+#endif
+
+/*
+** get_rsr128:
+**	mrrs	x0, x1, s3_0_c7_c4_0
+** ...
+*/
+__uint128_t
+get_rsr128 ()
+{
+  __arm_rsr128 ("par_el1");
+}
+
+/*
+** set_wsr128:
+** ...
+** 	msrr	s3_0_c7_c4_0, x0, x1
+** ...
+*/
+void
+set_wsr128 (__uint128_t c)
+{
+  __arm_wsr128 ("par_el1", c);
+}
+
+#pragma GCC pop_options
+
 /*
 ** get_rsr:
 ** ...