rs6000.md: Remove scratch reg on insns using addze and similar (plus (comparison r1 r2)...
* config/rs6000/rs6000.md: Remove scratch reg on insns using addze and similar (plus (comparison r1 r2) r3) insns. Add missing scratch reg in one case. Formatting fixes. From-SVN: r55695
This commit is contained in:
Alan Modra
Alan Modra
parent
d795dc906c
commit
097657c389
2 changed files with 158 additions and 201 deletions
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@ -1,3 +1,9 @@
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2002-07-24 Alan Modra <amodra@bigpond.net.au>
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* config/rs6000/rs6000.md: Remove scratch reg on insns using
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addze and similar (plus (comparison r1 r2) r3) insns. Add
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missing scratch reg in one case. Formatting fixes.
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2002-07-24 Neil Booth <neil@daikokuya.co.uk>
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* cppexp.c (parse_defined): Mark macro used.
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@ -11393,15 +11393,14 @@
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"")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
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(plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_short_operand" "r,O"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r")))
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(clobber (match_scratch:SI 4 "=&r,&r"))]
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(match_operand:SI 3 "gpc_reg_operand" "r,r")))]
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"TARGET_POWER"
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"@
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doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
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{srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
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doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
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{srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
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[(set_attr "length" "12")])
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(define_insn ""
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@ -11432,46 +11431,43 @@
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"TARGET_POWER && reload_completed"
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[(set (match_dup 4)
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(plus:SI (le:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
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(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
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(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_POWER"
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"@
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doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
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{srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
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doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
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{srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,12,16,16")])
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(define_split
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[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
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[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_scratch:SI 4 ""))]
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(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_POWER && reload_completed"
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[(parallel [(set (match_dup 0)
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[(set (match_dup 0)
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(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_dup 4))])
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(set (match_dup 5)
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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@ -11621,37 +11617,34 @@
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"")
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(define_insn ""
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[(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_scratch:SI 4 "=&r,&r"))]
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(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
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(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64"
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"@
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{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
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{sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "8,12")])
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(define_split
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[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
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[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_scratch:SI 4 ""))]
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(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64 && reload_completed"
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[(parallel [(set (match_dup 0)
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[(set (match_dup 0)
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(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_dup 4))])
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(set (match_dup 5)
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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@ -11665,14 +11658,13 @@
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[(set_attr "length" "12")])
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
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(and:SI (neg:SI
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(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "reg_or_short_operand" "rI")))
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(match_operand:SI 3 "gpc_reg_operand" "r")))
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(clobber (match_scratch:SI 4 "=&r"))]
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(match_operand:SI 3 "gpc_reg_operand" "r")))]
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"! TARGET_POWERPC64"
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"{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
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"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
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[(set_attr "length" "12")])
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(define_insn ""
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@ -11702,34 +11694,32 @@
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(clobber (match_scratch:SI 4 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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[(set (match_dup 4)
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(and:SI (neg:SI (leu:SI (match_dup 1)
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(match_dup 2)))
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(match_dup 3)))
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(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(and:SI (neg:SI
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(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
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(match_operand:SI 3 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
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(clobber (match_scratch:SI 4 "=&r,&r"))]
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(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
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(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
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"! TARGET_POWERPC64"
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"@
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{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
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{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,16")])
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(define_split
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[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
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[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(and:SI (neg:SI
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(leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
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@ -11737,13 +11727,12 @@
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
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(clobber (match_scratch:SI 4 ""))]
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(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
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"! TARGET_POWERPC64 && reload_completed"
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[(parallel [(set (match_dup 0)
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(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
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(clobber (match_dup 4))])
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(set (match_dup 5)
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[(set (match_dup 0)
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(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
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(match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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@ -11788,13 +11777,12 @@
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"")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
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(plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "reg_or_short_operand" "rI"))
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(match_operand:SI 3 "gpc_reg_operand" "r")))
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(clobber (match_scratch:SI 4 "=&r"))]
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(match_operand:SI 3 "gpc_reg_operand" "r")))]
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"TARGET_POWER"
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"doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
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"doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
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[(set_attr "length" "12")])
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(define_insn ""
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@ -11823,44 +11811,41 @@
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"TARGET_POWER && reload_completed"
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[(set (match_dup 4)
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(plus:SI (lt:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_scratch:SI 4 "=&r,&r"))]
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(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
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(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_POWER"
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"@
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doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
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doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,16")])
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(define_split
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[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
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[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_scratch:SI 4 ""))]
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(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"TARGET_POWER && reload_completed"
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[(parallel [(set (match_dup 0)
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[(set (match_dup 0)
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(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_dup 4))])
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(set (match_dup 5)
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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@ -11955,46 +11940,43 @@
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"! TARGET_POWERPC64 && reload_completed"
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[(set (match_dup 4)
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(plus:SI (ltu:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
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(compare:CC
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(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
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(match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
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(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
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(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
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(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64"
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"@
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{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
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{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
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{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
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{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
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#
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#"
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[(set_attr "type" "compare")
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(set_attr "length" "12,12,16,16")])
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(define_split
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[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
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[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
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(compare:CC
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(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_neg_short_operand" ""))
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(match_operand:SI 3 "gpc_reg_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 5)
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
|
@ -12045,21 +12027,20 @@
|
|||
(clobber (match_scratch:SI 3 ""))]
|
||||
"TARGET_POWER && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(ge:SI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_dup 3))])
|
||||
(ge:SI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_dup 3))])
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
|
||||
(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "rI"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r")))
|
||||
(clobber (match_scratch:SI 4 "=&r"))]
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r")))]
|
||||
"TARGET_POWER"
|
||||
"doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
|
||||
"doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
|
||||
[(set_attr "length" "12")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -12088,44 +12069,41 @@
|
|||
"TARGET_POWER && reload_completed"
|
||||
[(set (match_dup 4)
|
||||
(plus:SI (ge:SI (match_dup 1) (match_dup 2))
|
||||
(match_dup 3)))
|
||||
(match_dup 3)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 4)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC
|
||||
(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
|
||||
(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r"))]
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
|
||||
(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWER"
|
||||
"@
|
||||
doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
|
||||
doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "12,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "reg_or_short_operand" ""))
|
||||
(match_operand:SI 3 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWER && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 5)
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
|
@ -12270,39 +12248,36 @@
|
|||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
|
||||
(compare:CC
|
||||
(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
|
||||
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
|
||||
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
|
||||
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"! TARGET_POWERPC64"
|
||||
"@
|
||||
{sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
|
||||
{ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3
|
||||
{sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
|
||||
{ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "8,8,12,12")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "reg_or_neg_short_operand" ""))
|
||||
(match_operand:SI 3 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 5)
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
|
@ -12318,16 +12293,15 @@
|
|||
[(set_attr "length" "12")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
|
||||
(and:SI (neg:SI
|
||||
(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r")))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r"))]
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r")))]
|
||||
"! TARGET_POWERPC64"
|
||||
"@
|
||||
{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
|
||||
{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
|
||||
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
|
||||
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
|
||||
[(set_attr "length" "12")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -12359,36 +12333,34 @@
|
|||
(clobber (match_scratch:SI 4 ""))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 4)
|
||||
(and:SI (neg:SI (geu:SI (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(match_dup 3)))
|
||||
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
|
||||
(match_dup 3)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 4)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
|
||||
(compare:CC
|
||||
(and:SI (neg:SI
|
||||
(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
|
||||
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
|
||||
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
|
||||
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
|
||||
"! TARGET_POWERPC64"
|
||||
"@
|
||||
{sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
|
||||
{ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
|
||||
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
|
||||
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "12,12,16,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(and:SI (neg:SI
|
||||
(geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
|
|
@ -12396,13 +12368,11 @@
|
|||
(match_operand:SI 3 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 5)
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
|
@ -12534,13 +12504,12 @@
|
|||
[(set_attr "length" "12")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
|
||||
(plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
|
||||
(const_int 0))
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r")))
|
||||
(clobber (match_scratch:DI 3 "=&r"))]
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r")))]
|
||||
"TARGET_POWERPC64"
|
||||
"addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
|
||||
"addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
|
||||
[(set_attr "length" "12")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -12601,92 +12570,85 @@
|
|||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 3)
|
||||
(plus:DI (gt:DI (match_dup 1) (const_int 0))
|
||||
(match_dup 2)))
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 3)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC
|
||||
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
|
||||
(const_int 0))
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
|
||||
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
|
||||
(clobber (match_scratch:SI 3 "=&r,&r"))]
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
|
||||
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
|
||||
"! TARGET_POWERPC64"
|
||||
"@
|
||||
{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2
|
||||
{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "12,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(const_int 0))
|
||||
(match_operand:SI 2 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
|
||||
(clobber (match_scratch:SI 3 ""))]
|
||||
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
|
||||
(clobber (match_dup 3))])
|
||||
(set (match_dup 4)
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC
|
||||
(plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(const_int 0))
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
|
||||
(clobber (match_scratch:DI 3 "=&r,&r"))]
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
|
||||
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2
|
||||
addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "12,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(const_int 0))
|
||||
(match_operand:DI 2 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
|
||||
(clobber (match_scratch:DI 3 ""))]
|
||||
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
|
||||
(clobber (match_dup 3))])
|
||||
(set (match_dup 4)
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
|
||||
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r")))
|
||||
(clobber (match_scratch:SI 4 "=&r"))]
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r")))]
|
||||
"TARGET_POWER"
|
||||
"doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
|
||||
"doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
|
||||
[(set_attr "length" "12")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -12714,45 +12676,41 @@
|
|||
(clobber (match_scratch:SI 4 ""))]
|
||||
"TARGET_POWER && reload_completed"
|
||||
[(set (match_dup 4)
|
||||
(plus:SI (gt:SI (match_dup 1) (match_dup 2))
|
||||
(match_dup 3)))
|
||||
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 4)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC
|
||||
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "r,r"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
|
||||
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r"))]
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
|
||||
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWER"
|
||||
"@
|
||||
doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
|
||||
doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "12,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "reg_or_short_operand" ""))
|
||||
(match_operand:SI 3 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWER && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 5)
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
|
@ -12871,15 +12829,14 @@
|
|||
[(set_attr "length" "8,12")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
|
||||
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:DI 2 "reg_or_short_operand" "I,rI"))
|
||||
(match_operand:DI 3 "reg_or_short_operand" "r,rI")))
|
||||
(clobber (match_scratch:DI 4 "=&r,&r"))]
|
||||
(match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
addic %4,%1,%k2\;addze %0,%3
|
||||
subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
|
||||
addic %0,%1,%k2\;addze %0,%3
|
||||
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
|
||||
[(set_attr "length" "8,12")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -12910,7 +12867,7 @@
|
|||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 4)
|
||||
(plus:SI (gtu:SI (match_dup 1) (match_dup 2))
|
||||
(match_dup 3)))
|
||||
(match_dup 3)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 4)
|
||||
(const_int 0)))]
|
||||
|
|
@ -12951,77 +12908,71 @@
|
|||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
|
||||
(compare:CC
|
||||
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
|
||||
(match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
|
||||
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
|
||||
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"! TARGET_POWERPC64"
|
||||
"@
|
||||
{ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
|
||||
{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
|
||||
{ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
|
||||
{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "8,12,12,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "reg_or_short_operand" ""))
|
||||
(match_operand:SI 3 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "")
|
||||
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 4 ""))]
|
||||
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 5)
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
|
||||
(compare:CC
|
||||
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
|
||||
(match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
|
||||
(match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
|
||||
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
|
||||
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
addic %4,%1,%k2\;addze. %0,%3
|
||||
subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3
|
||||
addic %0,%1,%k2\;addze. %0,%3
|
||||
subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "compare")
|
||||
(set_attr "length" "8,12,12,16")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "reg_or_short_operand" ""))
|
||||
(match_operand:DI 3 "gpc_reg_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_scratch:DI 4 ""))]
|
||||
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
[(set (match_dup 0)
|
||||
(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 5)
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue