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ia64.md: Use define_constants for unspec numbers.

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* config/ia64/ia64.md: Use define_constants for unspec numbers.
        * config/ia64/ia64.c: Likewise.

From-SVN: r53344
This commit is contained in:
Richard Henderson 2002-05-09 13:58:35 -07:00 • committed by Richard Henderson
parent a8b4881f10
commit 086c0f96be
3 changed files with 131 additions and 106 deletions
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5
gcc/ChangeLog
View file

@ -1,3 +1,8 @@
2002-05-09 Richard Henderson <rth@redhat.com>
* config/ia64/ia64.md: Use define_constants for unspec numbers.
* config/ia64/ia64.c: Likewise.
2002-05-09 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_add_large_offset_to_sp): Remove FILE arg.

57
gcc/config/ia64/ia64.c
View file

@ -4576,8 +4576,8 @@ rtx_needs_barrier (x, flags, pred)
case UNSPEC:
switch (XINT (x, 1))
{
case 1: /* st8.spill */
case 2: /* ld8.fill */
case UNSPEC_GR_SPILL:
case UNSPEC_GR_RESTORE:
{
HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
HOST_WIDE_INT bit = (offset >> 3) & 63;
@ -4589,31 +4589,31 @@ rtx_needs_barrier (x, flags, pred)
break;
}
case 3: /* stf.spill */
case 4: /* ldf.spill */
case 8: /* popcnt */
case UNSPEC_FR_SPILL:
case UNSPEC_FR_RESTORE:
case UNSPEC_POPCNT:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
break;
case 7: /* pred_rel_mutex */
case 9: /* pic call */
case 12: /* mf */
case 19: /* fetchadd_acq */
case 20: /* mov = ar.bsp */
case 21: /* flushrs */
case 22: /* bundle selector */
case UNSPEC_PRED_REL_MUTEX:
case UNSPEC_PIC_CALL:
case UNSPEC_MF:
case UNSPEC_FETCHADD_ACQ:
case UNSPEC_BSP_VALUE:
case UNSPEC_FLUSHRS:
case UNSPEC_BUNDLE_SELECTOR:
break;
case 24: /* addp4 */
case UNSPEC_ADDP4:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
break;
case 5: /* recip_approx */
case UNSPEC_FR_RECIP_APPROX:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
break;
case 13: /* cmpxchg_acq */
case UNSPEC_CMPXCHG_ACQ:
need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
break;
@ -4626,7 +4626,7 @@ rtx_needs_barrier (x, flags, pred)
case UNSPEC_VOLATILE:
switch (XINT (x, 1))
{
case 0: /* alloc */
case UNSPECV_ALLOC:
/* Alloc must always be the first instruction of a group.
We force this by always returning true. */
/* ??? We might get better scheduling if we explicitly check for
@ -4640,17 +4640,15 @@ rtx_needs_barrier (x, flags, pred)
rws_access_regno (REG_AR_CFM, new_flags, pred);
return 1;
case 1: /* blockage */
case 2: /* insn group barrier */
return 0;
case 5: /* set_bsp */
case UNSPECV_SET_BSP:
need_barrier = 1;
break;
case 7: /* pred.rel.mutex */
case 8: /* safe_across_calls all */
case 9: /* safe_across_calls normal */
case UNSPECV_BLOCKAGE:
case UNSPECV_INSN_GROUP_BARRIER:
case UNSPECV_BREAK:
case UNSPECV_PSAC_ALL:
case UNSPECV_PSAC_NORMAL:
return 0;
default:
@ -4877,7 +4875,7 @@ emit_insn_group_barriers (dump, insns)
}
else if (GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
&& XINT (PATTERN (insn), 1) == 2)
&& XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
{
init_insn_group_barriers ();
last_label = 0;
@ -6646,7 +6644,7 @@ ia64_emit_nops ()
pat = INSN_P (insn) ? PATTERN (insn) : const0_rtx;
if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
continue;
if ((GET_CODE (pat) == UNSPEC && XINT (pat, 1) == 22)
if ((GET_CODE (pat) == UNSPEC && XINT (pat, 1) == UNSPEC_BUNDLE_SELECTOR)
|| GET_CODE (insn) == CODE_LABEL)
{
if (b)
@ -6662,7 +6660,8 @@ ia64_emit_nops ()
bundle_pos = 0;
continue;
}
else if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == 2)
else if (GET_CODE (pat) == UNSPEC_VOLATILE
&& XINT (pat, 1) == UNSPECV_INSN_GROUP_BARRIER)
{
int t = INTVAL (XVECEXP (pat, 0, 0));
if (b)
@ -6754,7 +6753,7 @@ ia64_reorg (insns)
insn = prev_active_insn (insn);
if (GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
&& XINT (PATTERN (insn), 1) == 2)
&& XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
{
saw_stop = 1;
insn = prev_active_insn (insn);
@ -6996,7 +6995,7 @@ process_set (asm_out_file, pat)
/* Look for the ALLOC insn. */
if (GET_CODE (src) == UNSPEC_VOLATILE
&& XINT (src, 1) == 0
&& XINT (src, 1) == UNSPECV_ALLOC
&& GET_CODE (dest) == REG)
{
dest_regno = REGNO (dest);

175
gcc/config/ia64/ia64.md
View file

@ -48,34 +48,34 @@
;; ??? Need a better way to describe alternate fp status registers.
;; Unspec usage:
;;
;; unspec:
;; 1 gr_spill
;; 2 gr_restore
;; 3 fr_spill
;; 4 fr_restore
;; 5 recip_approx
;; 7 pred_rel_mutex
;; 8 popcnt
;; 9 pic call
;; 12 mf
;; 13 cmpxchg_acq
;; 19 fetchadd_acq
;; 20 bsp_value
;; 21 flushrs
;; 22 bundle selector
;; 24 addp4
;; 25 prologue_use
;;
;; unspec_volatile:
;; 0 alloc
;; 1 blockage
;; 2 insn_group_barrier
;; 3 break
;; 5 set_bsp
;; 8 pred.safe_across_calls all
;; 9 pred.safe_across_calls normal
(define_constants
[(UNSPEC_GR_SPILL 1)
(UNSPEC_GR_RESTORE 2)
(UNSPEC_FR_SPILL 3)
(UNSPEC_FR_RESTORE 4)
(UNSPEC_FR_RECIP_APPROX 5)
(UNSPEC_PRED_REL_MUTEX 7)
(UNSPEC_POPCNT 8)
(UNSPEC_PIC_CALL 9)
(UNSPEC_MF 12)
(UNSPEC_CMPXCHG_ACQ 13)
(UNSPEC_FETCHADD_ACQ 19)
(UNSPEC_BSP_VALUE 20)
(UNSPEC_FLUSHRS 21)
(UNSPEC_BUNDLE_SELECTOR 22)
(UNSPEC_ADDP4 24)
(UNSPEC_PROLOGUE_USE 25)
])
(define_constants
[(UNSPECV_ALLOC 0)
(UNSPECV_BLOCKAGE 1)
(UNSPECV_INSN_GROUP_BARRIER 2)
(UNSPECV_BREAK 3)
(UNSPECV_SET_BSP 5)
(UNSPECV_PSAC_ALL 8) ; pred.safe_across_calls
(UNSPECV_PSAC_NORMAL 9)
])
;; ::::::::::::::::::::
;; ::
@ -261,7 +261,7 @@
&& GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))
(set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
(set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
"operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
@ -1288,7 +1288,7 @@
(set (match_dup 0) (const_int 1))
(cond_exec (ne (match_dup 2) (const_int 0))
(set (match_dup 0) (const_int 0)))
(set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
(set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
"operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
@ -1304,7 +1304,7 @@
(set (match_dup 0) (const_int 0)))
(cond_exec (eq (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 1)))
(set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
(set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
"")
(define_insn "*cmpsi_and_0"
@ -1692,7 +1692,7 @@
(set (match_operand:CCI 4 "register_operand" "")
(match_operand:CCI 5 "register_operand" ""))
(set (match_operand:BI 6 "register_operand" "")
(unspec:BI [(match_dup 6)] 7))]
(unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
"REGNO (operands[3]) == REGNO (operands[0])
&& REGNO (operands[4]) == REGNO (operands[0]) + 1
&& REGNO (operands[4]) == REGNO (operands[2]) + 1
@ -2005,7 +2005,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
@ -2260,7 +2261,7 @@
(set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
(set (match_dup 5) (const_int 0))
(set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
(set (match_dup 4) (unspec:DI [(match_dup 3)] 8))
(set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_POPCNT))
(set (match_operand:DI 0 "gr_register_operand" "")
(if_then_else:DI (ne (match_dup 6) (const_int 0))
(match_dup 5) (match_dup 4)))]
@ -2276,7 +2277,8 @@
(define_insn "*popcnt"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))]
(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")]
UNSPEC_POPCNT))]
""
"popcnt %0 = %1"
[(set_attr "itanium_class" "mmmul")])
@ -2389,7 +2391,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
(set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3)
@ -2447,7 +2450,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
@ -2616,7 +2620,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
@ -2670,7 +2675,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
@ -2921,7 +2927,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
(set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5))
(set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
@ -2998,7 +3005,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
@ -3394,7 +3402,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
(set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3)
@ -3471,7 +3480,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
@ -3545,7 +3555,7 @@
(match_operand:TF 3 "fr_register_operand" "f")))
(set (match_operand:BI 1 "register_operand" "=c")
(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
(match_dup 3)] 5))
(match_dup 3)] UNSPEC_FR_RECIP_APPROX))
(use (match_operand:SI 4 "const_int_operand" ""))]
"INTEL_EXTENDED_IEEE_FORMAT"
"frcpa.s%4 %0, %1 = %2, %3"
@ -4682,7 +4692,7 @@
(define_insn "call_pic"
[(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
(match_operand 1 "" ""))
(use (unspec [(reg:DI 1)] 9))
(use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
(clobber (match_operand:DI 2 "register_operand" "=b,b"))]
""
"br.call%+.many %2 = %0"
@ -4692,7 +4702,7 @@
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
(match_operand 2 "" "")))
(use (unspec [(reg:DI 1)] 9))
(use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
(clobber (match_operand:DI 3 "register_operand" "=b,b"))]
""
"br.call%+.many %3 = %1"
@ -4701,7 +4711,7 @@
(define_insn "sibcall_pic"
[(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
(match_operand 1 "" ""))
(use (unspec [(reg:DI 1)] 9))
(use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL))
(use (match_operand:DI 2 "register_operand" "=b"))
(use (match_operand:DI 3 "ar_pfs_reg_operand" ""))]
""
@ -4871,7 +4881,7 @@
(define_insn "alloc"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(const_int 0)] 0))
(unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
(use (match_operand:DI 1 "const_int_operand" "i"))
(use (match_operand:DI 2 "const_int_operand" "i"))
(use (match_operand:DI 3 "const_int_operand" "i"))
@ -4885,7 +4895,8 @@
(define_expand "gr_spill"
[(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "const_int_operand" "")] 1))
(match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_SPILL))
(clobber (match_dup 3))])]
""
"operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
@ -4893,7 +4904,8 @@
(define_insn "gr_spill_internal"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "const_int_operand" "")] 1))
(match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_SPILL))
(clobber (match_operand:DI 3 "register_operand" ""))]
""
"*
@ -4906,7 +4918,8 @@
(define_expand "gr_restore"
[(parallel [(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
(match_operand:DI 2 "const_int_operand" "")] 2))
(match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_RESTORE))
(use (match_dup 3))])]
""
"operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
@ -4914,7 +4927,8 @@
(define_insn "gr_restore_internal"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
(match_operand:DI 2 "const_int_operand" "")] 2))
(match_operand:DI 2 "const_int_operand" "")]
UNSPEC_GR_RESTORE))
(use (match_operand:DI 3 "register_operand" ""))]
""
"*
@ -4925,14 +4939,16 @@
(define_insn "fr_spill"
[(set (match_operand:TF 0 "memory_operand" "=m")
(unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))]
(unspec:TF [(match_operand:TF 1 "register_operand" "f")]
UNSPEC_FR_SPILL))]
""
"stf.spill %0 = %1%P0"
[(set_attr "itanium_class" "stf")])
(define_insn "fr_restore"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))]
(unspec:TF [(match_operand:TF 1 "memory_operand" "m")]
UNSPEC_FR_RESTORE))]
""
"ldf.fill %0 = %1%P1"
[(set_attr "itanium_class" "fld")])
@ -4943,13 +4959,14 @@
(define_insn "bsp_value"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(const_int 0)] 20))]
(unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
""
";;\;mov %0 = ar.bsp"
[(set_attr "itanium_class" "frar_i")])
(define_insn "set_bsp"
[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)]
[(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
UNSPECV_SET_BSP)]
""
"flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
[(set_attr "itanium_class" "unknown")
@ -4960,7 +4977,7 @@
;; fixed later. This avoids an RSE DV.
(define_insn "flushrs"
[(unspec [(const_int 0)] 21)]
[(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
""
";;\;flushrs\;;;"
[(set_attr "itanium_class" "rse_m")])
@ -5012,7 +5029,7 @@
[(set_attr "itanium_class" "nop_x")])
(define_insn "bundle_selector"
[(unspec [(match_operand 0 "const_int_operand" "")] 22)]
[(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
""
"*
{
@ -5024,14 +5041,15 @@
;; Pseudo instruction that prevents the scheduler from moving code above this
;; point.
(define_insn "blockage"
[(unspec_volatile [(const_int 0)] 1)]
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
""
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
(define_insn "insn_group_barrier"
[(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)]
[(unspec_volatile [(match_operand 0 "const_int_operand" "")]
UNSPECV_INSN_GROUP_BARRIER)]
""
";;"
[(set_attr "itanium_class" "stop_bit")
@ -5069,7 +5087,7 @@
(set_attr "predicable" "no")])
(define_insn "break_f"
[(unspec_volatile [(const_int 0)] 3)]
[(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
""
"break.f 0"
[(set_attr "itanium_class" "nop_f")])
@ -5204,7 +5222,7 @@
(define_expand "mf"
[(set (mem:BLK (match_dup 0))
(unspec:BLK [(mem:BLK (match_dup 0))] 12))]
(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
""
"
{
@ -5214,7 +5232,7 @@
(define_insn "*mf_internal"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_operand:BLK 1 "" "")] 12))]
(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
""
"mf"
[(set_attr "itanium_class" "syst_m")])
@ -5224,7 +5242,8 @@
(match_dup 1))
(set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
(unspec:SI [(match_dup 1)
(match_operand:SI 2 "fetchadd_operand" "n")] 19))]
(match_operand:SI 2 "fetchadd_operand" "n")]
UNSPEC_FETCHADD_ACQ))]
""
"fetchadd4.acq %0 = %1, %2"
[(set_attr "itanium_class" "sem")])
@ -5234,7 +5253,8 @@
(match_dup 1))
(set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
(unspec:DI [(match_dup 1)
(match_operand:DI 2 "fetchadd_operand" "n")] 19))]
(match_operand:DI 2 "fetchadd_operand" "n")]
UNSPEC_FETCHADD_ACQ))]
""
"fetchadd8.acq %0 = %1, %2"
[(set_attr "itanium_class" "sem")])
@ -5245,7 +5265,8 @@
(set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
(unspec:SI [(match_dup 1)
(match_operand:SI 2 "gr_register_operand" "r")
(match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))]
(match_operand:SI 3 "ar_ccv_reg_operand" "")]
UNSPEC_CMPXCHG_ACQ))]
""
"cmpxchg4.acq %0 = %1, %2, %3"
[(set_attr "itanium_class" "sem")])
@ -5256,7 +5277,8 @@
(set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
(unspec:DI [(match_dup 1)
(match_operand:DI 2 "gr_register_operand" "r")
(match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))]
(match_operand:DI 3 "ar_ccv_reg_operand" "")]
UNSPEC_CMPXCHG_ACQ))]
""
"cmpxchg8.acq %0 = %1, %2, %3"
[(set_attr "itanium_class" "sem")])
@ -5290,21 +5312,21 @@
(define_insn "pred_rel_mutex"
[(set (match_operand:BI 0 "register_operand" "+c")
(unspec:BI [(match_dup 0)] 7))]
(unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
""
".pred.rel.mutex %0, %I0"
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
(define_insn "safe_across_calls_all"
[(unspec_volatile [(const_int 0)] 8)]
[(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
""
".pred.safe_across_calls p1-p63"
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
(define_insn "safe_across_calls_normal"
[(unspec_volatile [(const_int 0)] 9)]
[(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
""
"*
{
@ -5314,14 +5336,13 @@
[(set_attr "itanium_class" "ignore")
(set_attr "predicable" "no")])
;;
;;
;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
;; pointer. This is used by the HP-UX 32 bit mode.
(define_insn "ptr_extend"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] 24))]
(unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
UNSPEC_ADDP4))]
""
"addp4 %0 = 0,%1"
[(set_attr "itanium_class" "ialu")])
@ -5334,7 +5355,7 @@
(unspec:DI
[(plus:SI (match_operand:SI 1 "basereg_operand" "r")
(match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
24))]
UNSPEC_ADDP4))]
""
"addp4 %0 = %2, %1"
[(set_attr "itanium_class" "ialu")])
@ -5344,16 +5365,16 @@
(unspec:DI
[(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
(match_operand:SI 2 "basereg_operand" "r"))]
24))]
UNSPEC_ADDP4))]
""
"addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")])
;;
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling
(define_insn "prologue_use"
[(unspec:DI [(match_operand:DI 0 "register_operand" "")] 25)]
[(unspec:DI [(match_operand:DI 0 "register_operand" "")]
UNSPEC_PROLOGUE_USE)]
""
"// %0 needed for EH"
[(set_attr "itanium_class" "ignore")