[RISC-V][PR target/106544] Avoid ICEs due to bogus asms
This is a fix for a bug Andrew P filed a while back where essentially a poorly crafted asm statement could trigger a ICE during assembly output. Various cases will use INTVAL (op) without verifying the operand is a CONST_INT node first. The usual way to handle this is via output_operand_lossage, which this patch implements. I focused primarily on the CONST_INT cases, there could well be other problems in this space, if so they should get distinct bugs with testcases. Tested in my tester on rv32 and rv64. Waiting for pre-commit testing before moving forward. PR target/106544 gcc/ * config/riscv/riscv.cc (riscv_print_operand): Issue an error for invalid operands rather than invalidly accessing INTVAL of an object that is not a CONST_INT. Fix one error string for 'N'. gcc/testsuite * gcc.target/riscv/pr106544.c: New test.
This commit is contained in:
Jeff Law
parent
efc0981077
commit
07e532a060
2 changed files with 104 additions and 71 deletions
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@ -7009,62 +7009,77 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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fputs (GET_RTX_NAME (reverse_condition (code)), file);
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break;
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case 'A': {
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const enum memmodel model = memmodel_base (INTVAL (op));
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if (riscv_memmodel_needs_amo_acquire (model)
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&& riscv_memmodel_needs_amo_release (model))
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fputs (".aqrl", file);
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else if (riscv_memmodel_needs_amo_acquire (model))
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fputs (".aq", file);
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else if (riscv_memmodel_needs_amo_release (model))
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fputs (".rl", file);
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case 'A':
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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const enum memmodel model = memmodel_base (INTVAL (op));
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if (riscv_memmodel_needs_amo_acquire (model)
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&& riscv_memmodel_needs_amo_release (model))
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fputs (".aqrl", file);
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else if (riscv_memmodel_needs_amo_acquire (model))
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fputs (".aq", file);
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else if (riscv_memmodel_needs_amo_release (model))
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fputs (".rl", file);
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}
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break;
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}
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case 'I': {
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const enum memmodel model = memmodel_base (INTVAL (op));
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if (TARGET_ZTSO && model != MEMMODEL_SEQ_CST)
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/* LR ops only have an annotation for SEQ_CST in the Ztso mapping. */
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break;
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else if (model == MEMMODEL_SEQ_CST)
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fputs (".aqrl", file);
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else if (riscv_memmodel_needs_amo_acquire (model))
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fputs (".aq", file);
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case 'I':
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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const enum memmodel model = memmodel_base (INTVAL (op));
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if (TARGET_ZTSO && model != MEMMODEL_SEQ_CST)
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/* LR ops only have an annotation for SEQ_CST in the Ztso mapping. */
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break;
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else if (model == MEMMODEL_SEQ_CST)
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fputs (".aqrl", file);
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else if (riscv_memmodel_needs_amo_acquire (model))
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fputs (".aq", file);
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}
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break;
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}
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case 'J': {
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const enum memmodel model = memmodel_base (INTVAL (op));
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if (TARGET_ZTSO && model == MEMMODEL_SEQ_CST)
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/* SC ops only have an annotation for SEQ_CST in the Ztso mapping. */
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fputs (".rl", file);
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else if (TARGET_ZTSO)
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break;
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else if (riscv_memmodel_needs_amo_release (model))
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fputs (".rl", file);
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case 'J':
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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const enum memmodel model = memmodel_base (INTVAL (op));
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if (TARGET_ZTSO && model == MEMMODEL_SEQ_CST)
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/* SC ops only have an annotation for SEQ_CST in the Ztso mapping. */
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fputs (".rl", file);
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else if (TARGET_ZTSO)
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break;
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else if (riscv_memmodel_needs_amo_release (model))
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fputs (".rl", file);
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}
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break;
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}
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case 'L':
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{
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const char *ntl_hint = NULL;
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switch (INTVAL (op))
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{
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case 0:
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ntl_hint = "ntl.all";
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break;
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case 1:
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ntl_hint = "ntl.pall";
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break;
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case 2:
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ntl_hint = "ntl.p1";
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break;
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}
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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const char *ntl_hint = NULL;
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switch (INTVAL (op))
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{
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case 0:
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ntl_hint = "ntl.all";
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break;
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case 1:
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ntl_hint = "ntl.pall";
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break;
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case 2:
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ntl_hint = "ntl.p1";
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break;
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}
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if (ntl_hint)
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asm_fprintf (file, "%s\n\t", ntl_hint);
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if (ntl_hint)
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asm_fprintf (file, "%s\n\t", ntl_hint);
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}
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break;
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}
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case 'i':
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if (code != REG)
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@ -7076,32 +7091,44 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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break;
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case 'S':
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{
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rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
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output_addr_const (file, newop);
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break;
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}
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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rtx newop = GEN_INT (ctz_hwi (INTVAL (op)));
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output_addr_const (file, newop);
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}
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break;
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case 'T':
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{
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rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
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output_addr_const (file, newop);
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break;
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}
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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rtx newop = GEN_INT (ctz_hwi (~INTVAL (op)));
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output_addr_const (file, newop);
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}
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break;
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case 'X':
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{
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int ival = INTVAL (op) + 1;
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rtx newop = GEN_INT (ctz_hwi (ival) + 1);
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output_addr_const (file, newop);
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break;
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}
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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int ival = INTVAL (op) + 1;
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rtx newop = GEN_INT (ctz_hwi (ival) + 1);
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output_addr_const (file, newop);
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}
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break;
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case 'Y':
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{
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unsigned int imm = (UINTVAL (op) & 63);
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gcc_assert (imm <= 63);
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rtx newop = GEN_INT (imm);
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output_addr_const (file, newop);
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break;
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}
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if (!CONST_INT_P (op))
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output_operand_lossage ("invalid operand for '%%%c'", letter);
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else
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{
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unsigned int imm = (UINTVAL (op) & 63);
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gcc_assert (imm <= 63);
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rtx newop = GEN_INT (imm);
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output_addr_const (file, newop);
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}
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break;
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case 'N':
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{
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if (!REG_P(op))
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@ -7119,7 +7146,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
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else if (IN_RANGE (regno, V_REG_FIRST, V_REG_LAST))
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offset = V_REG_FIRST;
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else
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output_operand_lossage ("invalid register number for 'N' modifie");
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output_operand_lossage ("invalid register number for 'N' modifier");
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asm_fprintf (file, "%u", (regno - offset));
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break;
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6
gcc/testsuite/gcc.target/riscv/pr106544.c
Normal file
6
gcc/testsuite/gcc.target/riscv/pr106544.c
Normal file
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@ -0,0 +1,6 @@
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/* { dg-do compile } */
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/* { dg-skip-if "" { *-*-* } { "-flto"} } */
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void f(int a)
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{
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__asm("#%A0" : : "r"(a)); /* { dg-error "invalid 'asm': invalid operand" } */
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}
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