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rs6000: Simplify "switch (which_alternative)" patterns

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A few of the rs6000 patterns use C code as output control string, where
that code is just a "switch (which_alternative)" with all alternatives
returning a constant string or just the result of a function call as
template.
Write such cases as just a list of templates, with the few pieces that
are C code preceded by "*".


	* config/rs6000/altivec.md (*altivec_mov<mode>): Write the output
	control string as a list of templates instead of as C code.
	(*altivec_movti): Ditto.
	* config/rs6000/darwin.md (movdf_low_di): Ditto.

From-SVN: r264587
This commit is contained in:
Segher Boessenkool 2018-09-26 01:31:22 +02:00 • committed by Segher Boessenkool
parent ad117173a0
commit 07a38de7ce
3 changed files with 29 additions and 40 deletions
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7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2018-09-25 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md (*altivec_mov<mode>): Write the output
control string as a list of templates instead of as C code.
(*altivec_movti): Ditto.
* config/rs6000/darwin.md (movdf_low_di): Ditto.
2018-09-25 Jim Wilson <jimw@sifive.com>
* config/riscv/riscv.c (riscv_split_symbol): Mark auipc label as weak

48
gcc/config/rs6000/altivec.md
View file

@ -245,21 +245,16 @@
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
{
switch (which_alternative)
{
case 0: return "stvx %1,%y0";
case 1: return "lvx %0,%y1";
case 2: return "vor %0,%1,%1";
case 3: return "#";
case 4: return "#";
case 5: return "#";
case 6: return "vxor %0,%0,%0";
case 7: return output_vec_const_move (operands);
case 8: return "#";
default: gcc_unreachable ();
}
}
"@
stvx %1,%y0
lvx %0,%y1
vor %0,%1,%1
#
#
#
vxor %0,%0,%0
* return output_vec_const_move (operands);
#"
[(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*,*")
(set_attr "length" "4,4,4,20,20,20,4,8,32")])
@ -272,20 +267,15 @@
"VECTOR_MEM_ALTIVEC_P (TImode)
&& (register_operand (operands[0], TImode)
|| register_operand (operands[1], TImode))"
{
switch (which_alternative)
{
case 0: return "stvx %1,%y0";
case 1: return "lvx %0,%y1";
case 2: return "vor %0,%1,%1";
case 3: return "#";
case 4: return "#";
case 5: return "#";
case 6: return "vxor %0,%0,%0";
case 7: return output_vec_const_move (operands);
default: gcc_unreachable ();
}
}
"@
stvx %1,%y0
lvx %0,%y1
vor %0,%1,%1
#
#
#
vxor %0,%0,%0
* return output_vec_const_move (operands);"
[(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*")])
;; Load up a vector with the most significant bit set by loading up -1 and

14
gcc/config/rs6000/darwin.md
View file

@ -60,17 +60,9 @@ You should have received a copy of the GNU General Public License
(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
{
switch (which_alternative)
{
case 0:
return "lfd %0,lo16(%2)(%1)";
case 1:
return "ld %0,lo16(%2)(%1)";
default:
gcc_unreachable ();
}
}
"@
lfd %0,lo16(%2)(%1)
ld %0,lo16(%2)(%1)"
[(set_attr "type" "load")])
(define_insn "movdf_low_st_si"