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RISC-V: Emit "i" suffix for instructions with immediate operands

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This changes makes GCC asm output use instruction names that are
consistent with the RISC-V ISA manual.  The assembler accepts
immediate-operand instructions without the "i" suffix, so this all
worked before, it's just a bit cleaner to match the ISA manual more
closely.

gcc/ChangeLog

2017-10-03  Michael Clark  <michaeljclark@mac.com>

        * config/riscv/riscv.c (riscv_print_operand): Add a 'i' format.
        config/riscv/riscv.md (addsi3): Use 'i' for immediates.
        (adddi3): Likewise.
        (*addsi3_extended): Likewise.
        (*addsi3_extended2): Likewise.
        (<optab>si3): Likewise.
        (<optab>di3): Likewise.
        (<optab><mode>3): Likewise.
        (<*optabe>si3_internal): Likewise.
        (zero_extendqi<SUPERQI:mode>2): Likewise.
        (*add<mode>hi3): Likewise.
        (*xor<mode>hi3): Likewise.
        (<optab>di3): Likewise.
        (*<optab>si3_extend): Likewise.
        (*sge<u>_<X:mode><GPR:mode>): Likewise.
        (*slt<u>_<X:mode><GPR:mode>): Likewise.
        (*sle<u>_<X:mode><GPR:mode>): Likewise.

From-SVN: r254418
This commit is contained in:
Michael Clark 2017-11-05 00:42:54 +00:00 • committed by Palmer Dabbelt
parent caf1c1cd12
commit 0791ac186b
3 changed files with 45 additions and 19 deletions
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20
gcc/ChangeLog
View file

@ -1,3 +1,23 @@
2017-11-04 Michael Clark <michaeljclark@mac.com>
* config/riscv/riscv.c (riscv_print_operand): Add a 'i' format.
config/riscv/riscv.md (addsi3): Use 'i' for immediates.
(adddi3): Likewise.
(*addsi3_extended): Likewise.
(*addsi3_extended2): Likewise.
(<optab>si3): Likewise.
(<optab>di3): Likewise.
(<optab><mode>3): Likewise.
(<*optabe>si3_internal): Likewise.
(zero_extendqi<SUPERQI:mode>2): Likewise.
(*add<mode>hi3): Likewise.
(*xor<mode>hi3): Likewise.
(<optab>di3): Likewise.
(*<optab>si3_extend): Likewise.
(*sge<u>_<X:mode><GPR:mode>): Likewise.
(*slt<u>_<X:mode><GPR:mode>): Likewise.
(*sle<u>_<X:mode><GPR:mode>): Likewise.
2017-11-04 Andrew Waterman <andrew@sifive.com>
* config/riscv/riscv.c (riscv_option_override): Conditionally set

8
gcc/config/riscv/riscv.c
View file

@ -2733,7 +2733,8 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
'C' Print the integer branch condition for comparison OP.
'A' Print the atomic operation suffix for memory model OP.
'F' Print a FENCE if the memory model requires a release.
'z' Print x0 if OP is zero, otherwise print OP normally. */
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register. */
static void
riscv_print_operand (FILE *file, rtx op, int letter)
@ -2768,6 +2769,11 @@ riscv_print_operand (FILE *file, rtx op, int letter)
fputs ("fence iorw,ow; ", file);
break;
case 'i':
if (code != REG)
fputs ("i", file);
break;
default:
switch (code)
{

36
gcc/config/riscv/riscv.md
View file

@ -414,7 +414,7 @@
(plus:SI (match_operand:SI 1 "register_operand" " r,r")
(match_operand:SI 2 "arith_operand" " r,I")))]
""
{ return TARGET_64BIT ? "addw\t%0,%1,%2" : "add\t%0,%1,%2"; }
{ return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; }
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@ -423,7 +423,7 @@
(plus:DI (match_operand:DI 1 "register_operand" " r,r")
(match_operand:DI 2 "arith_operand" " r,I")))]
"TARGET_64BIT"
"add\t%0,%1,%2"
"add%i2\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
@ -433,7 +433,7 @@
(plus:SI (match_operand:SI 1 "register_operand" " r,r")
(match_operand:SI 2 "arith_operand" " r,I"))))]
"TARGET_64BIT"
"addw\t%0,%1,%2"
"add%i2w\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@ -444,7 +444,7 @@
(match_operand:DI 2 "arith_operand" " r,I"))
0)))]
"TARGET_64BIT"
"addw\t%0,%1,%2"
"add%i2w\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@ -705,7 +705,7 @@
(any_div:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
"TARGET_DIV"
{ return TARGET_64BIT ? "<insn>w\t%0,%1,%2" : "<insn>\t%0,%1,%2"; }
{ return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2"; }
[(set_attr "type" "idiv")
(set_attr "mode" "SI")])
@ -714,7 +714,7 @@
(any_div:DI (match_operand:DI 1 "register_operand" " r")
(match_operand:DI 2 "register_operand" " r")))]
"TARGET_DIV && TARGET_64BIT"
"<insn>\t%0,%1,%2"
"<insn>%i2\t%0,%1,%2"
[(set_attr "type" "idiv")
(set_attr "mode" "DI")])
@ -724,7 +724,7 @@
(any_div:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r"))))]
"TARGET_DIV && TARGET_64BIT"
"<insn>w\t%0,%1,%2"
"<insn>%i2w\t%0,%1,%2"
[(set_attr "type" "idiv")
(set_attr "mode" "DI")])
@ -928,7 +928,7 @@
(any_bitwise:X (match_operand:X 1 "register_operand" "%r,r")
(match_operand:X 2 "arith_operand" " r,I")))]
""
"<insn>\t%0,%1,%2"
"<insn>%i2\t%0,%1,%2"
[(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
@ -937,7 +937,7 @@
(any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r")
(match_operand:SI 2 "arith_operand" " r,I")))]
"TARGET_64BIT"
"<insn>\t%0,%1,%2"
"<insn>%i2\t%0,%1,%2"
[(set_attr "type" "logical")
(set_attr "mode" "SI")])
@ -1025,7 +1025,7 @@
(match_operand:QI 1 "nonimmediate_operand" " r,m")))]
""
"@
and\t%0,%1,0xff
andi\t%0,%1,0xff
lbu\t%0,%1"
[(set_attr "move_type" "andi,load")
(set_attr "mode" "<SUPERQI:MODE>")])
@ -1318,7 +1318,7 @@
(plus:HI (match_operand:HISI 1 "register_operand" " r,r")
(match_operand:HISI 2 "arith_operand" " r,I")))]
""
{ return TARGET_64BIT ? "addw\t%0,%1,%2" : "add\t%0,%1,%2"; }
{ return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; }
[(set_attr "type" "arith")
(set_attr "mode" "HI")])
@ -1327,7 +1327,7 @@
(xor:HI (match_operand:HISI 1 "register_operand" " r,r")
(match_operand:HISI 2 "arith_operand" " r,I")))]
""
"xor\t%0,%1,%2"
"xor%i2\t%0,%1,%2"
[(set_attr "type" "logical")
(set_attr "mode" "HI")])
@ -1475,7 +1475,7 @@
operands[2] = GEN_INT (INTVAL (operands[2])
& (GET_MODE_BITSIZE (SImode) - 1));
return TARGET_64BIT ? "<insn>w\t%0,%1,%2" : "<insn>\t%0,%1,%2";
return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2";
}
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
@ -1491,7 +1491,7 @@
operands[2] = GEN_INT (INTVAL (operands[2])
& (GET_MODE_BITSIZE (DImode) - 1));
return "<insn>\t%0,%1,%2";
return "<insn>%i2\t%0,%1,%2";
}
[(set_attr "type" "shift")
(set_attr "mode" "DI")])
@ -1506,7 +1506,7 @@
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "<insn>w\t%0,%1,%2";
return "<insn>%i2w\t%0,%1,%2";
}
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
@ -1725,7 +1725,7 @@
(any_ge:GPR (match_operand:X 1 "register_operand" " r")
(const_int 1)))]
""
"slt<u>\t%0,zero,%1"
"slt%i2<u>\t%0,zero,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
@ -1734,7 +1734,7 @@
(any_lt:GPR (match_operand:X 1 "register_operand" " r")
(match_operand:X 2 "arith_operand" " rI")))]
""
"slt<u>\t%0,%1,%2"
"slt%i2<u>\t%0,%1,%2"
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])
@ -1745,7 +1745,7 @@
""
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "slt<u>\t%0,%1,%2";
return "slt%i2<u>\t%0,%1,%2";
}
[(set_attr "type" "slt")
(set_attr "mode" "<MODE>")])