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Enable tuning options for skylake-avx512.

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gcc/
	PR target/84413
	* x86-tune.def (movx, partial_reg_dependency): Enable for
	m_SKYLAKE_AVX512.

From-SVN: r258972
This commit is contained in:
Julia Koval 2018-03-30 09:04:55 +02:00 • committed by Julia Koval
parent 9cffc5a73a
commit 06be18e782
2 changed files with 8 additions and 2 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2018-03-30 Julia Koval <julia.koval@intel.com>
PR target/84413
* x86-tune.def (movx, partial_reg_dependency): Enable for
m_SKYLAKE_AVX512.
2018-03-29 Vladimir Makarov <vmakarov@redhat.com>
PR inline-asm/84985

4
gcc/config/i386/x86-tune.def
View file

@ -50,7 +50,7 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_KNM | m_AMD_MULTIPLE | m_GENERIC)
| m_KNL | m_KNM | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
destinations to be 128bit to allow register renaming on 128bit SSE units,
@ -85,7 +85,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
DEF_TUNE (X86_TUNE_MOVX, "movx",
m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
| m_GEODE | m_AMD_MULTIPLE | m_GENERIC)
| m_GEODE | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC)
/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
full sized loads. */