i386.md (ARGP_REG, [...]): New.
* config/i386/i386.md (ARGP_REG, FRAME_REG, BND2_REG, BND3_REG, FIRST_PSEUDO_REG): New. * config/i386/i386.h (STACK_POINTER_REGNUM): Define to SP_REG. (ARG_POINTER_REGNUM): Define to ARGP_REG. (FRAME_POINTER_REGNUM): Define to FRAME_REG. (HARD_FRAME_POINTER_REGNUM): Define to BP_REG. (FIRST_PSEUDO_REGISTER): Define to FIRST_PSEUDO_REG. (FIRST_INT_REG): New. (LAST_INT_REG): New. (FIRST_*_REG): Define using *_REG. (LAST_*_REG): Ditto. (QI_REGNO_P): Define using FIRST_QU_REG and LAST_QI_REG. (LEGACY_INT_REGNO_P): Define using FIRST_INT_REG and LAST_INT_REG. (FIRST_FLOAT_REG): Define to FIRST_STACK_REG. From-SVN: r222269
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
35430ca0c6
commit
05416670a6
3 changed files with 81 additions and 56 deletions
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@ -1,3 +1,20 @@
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2015-04-21 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (ARGP_REG, FRAME_REG, BND2_REG, BND3_REG,
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FIRST_PSEUDO_REG): New.
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* config/i386/i386.h (STACK_POINTER_REGNUM): Define to SP_REG.
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(ARG_POINTER_REGNUM): Define to ARGP_REG.
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(FRAME_POINTER_REGNUM): Define to FRAME_REG.
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(HARD_FRAME_POINTER_REGNUM): Define to BP_REG.
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(FIRST_PSEUDO_REGISTER): Define to FIRST_PSEUDO_REG.
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(FIRST_INT_REG): New.
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(LAST_INT_REG): New.
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(FIRST_*_REG): Define using *_REG.
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(LAST_*_REG): Ditto.
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(QI_REGNO_P): Define using FIRST_QU_REG and LAST_QI_REG.
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(LEGACY_INT_REGNO_P): Define using FIRST_INT_REG and LAST_INT_REG.
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(FIRST_FLOAT_REG): Define to FIRST_STACK_REG.
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2015-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* expmed.c: (synth_mult): Only assume overlapping
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@ -957,7 +957,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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eliminated during reloading in favor of either the stack or frame
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pointer. */
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#define FIRST_PSEUDO_REGISTER 81
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#define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG
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/* Number of hardware registers that go into the DWARF-2 unwind info.
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If not defined, equals FIRST_PSEUDO_REGISTER. */
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@ -1100,7 +1100,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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|| (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
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|| (MODE) == V4TImode)
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#define VALID_AVX512VL_128_REG_MODE(MODE) \
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#define VALID_AVX512VL_128_REG_MODE(MODE) \
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((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
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|| (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode)
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@ -1121,6 +1121,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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|| (MODE) == V2SImode || (MODE) == SImode \
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|| (MODE) == V4HImode || (MODE) == V8QImode)
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#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
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#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
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#define VALID_BND_REG_MODE(MODE) \
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(TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode)
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@ -1150,9 +1154,15 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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|| (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
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|| (MODE) == V16SFmode)
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#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
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#define X87_FLOAT_MODE_P(MODE) \
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(TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
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#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
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#define SSE_FLOAT_MODE_P(MODE) \
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((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
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#define FMA4_VEC_FLOAT_MODE_P(MODE) \
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(TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
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|| (MODE) == V8SFmode || (MODE) == V4DFmode))
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
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@ -1198,42 +1208,46 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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register. The ordinary mov instructions won't work */
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/* #define PC_REGNUM */
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM ARGP_REG
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/* Register to use for pushing function arguments. */
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#define STACK_POINTER_REGNUM 7
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#define STACK_POINTER_REGNUM SP_REG
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/* Base register for access to local variables of the function. */
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#define HARD_FRAME_POINTER_REGNUM 6
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#define FRAME_POINTER_REGNUM FRAME_REG
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#define HARD_FRAME_POINTER_REGNUM BP_REG
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/* Base register for access to local variables of the function. */
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#define FRAME_POINTER_REGNUM 20
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#define FIRST_INT_REG AX_REG
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#define LAST_INT_REG SP_REG
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/* First floating point reg */
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#define FIRST_FLOAT_REG 8
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#define FIRST_QI_REG AX_REG
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#define LAST_QI_REG BX_REG
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/* First & last stack-like regs */
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#define FIRST_STACK_REG FIRST_FLOAT_REG
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#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
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#define FIRST_STACK_REG ST0_REG
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#define LAST_STACK_REG ST7_REG
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#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
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#define LAST_SSE_REG (FIRST_SSE_REG + 7)
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#define FIRST_SSE_REG XMM0_REG
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#define LAST_SSE_REG XMM7_REG
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#define FIRST_MMX_REG (LAST_SSE_REG + 1) /*29*/
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#define LAST_MMX_REG (FIRST_MMX_REG + 7)
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#define FIRST_MMX_REG MM0_REG
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#define LAST_MMX_REG MM7_REG
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#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) /*37*/
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#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
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#define FIRST_REX_INT_REG R8_REG
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#define LAST_REX_INT_REG R15_REG
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#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) /*45*/
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#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
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#define FIRST_REX_SSE_REG XMM8_REG
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#define LAST_REX_SSE_REG XMM15_REG
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#define FIRST_EXT_REX_SSE_REG (LAST_REX_SSE_REG + 1) /*53*/
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#define LAST_EXT_REX_SSE_REG (FIRST_EXT_REX_SSE_REG + 15) /*68*/
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#define FIRST_EXT_REX_SSE_REG XMM16_REG
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#define LAST_EXT_REX_SSE_REG XMM31_REG
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#define FIRST_MASK_REG (LAST_EXT_REX_SSE_REG + 1) /*69*/
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#define LAST_MASK_REG (FIRST_MASK_REG + 7) /*76*/
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#define FIRST_MASK_REG MASK0_REG
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#define LAST_MASK_REG MASK7_REG
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#define FIRST_BND_REG (LAST_MASK_REG + 1) /*77*/
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#define LAST_BND_REG (FIRST_BND_REG + 3) /*80*/
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#define FIRST_BND_REG BND0_REG
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#define LAST_BND_REG BND3_REG
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/* Override this in other tm.h files to cope with various OS lossage
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requiring a frame pointer. */
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@ -1244,9 +1258,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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/* Make sure we can access arbitrary call frames. */
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#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM 16
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/* Register to hold the addressing base for position independent
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code access to data items. We don't use PIC pointer for 64bit
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mode. Define the regnum to dummy value to prevent gcc from
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@ -1444,7 +1455,14 @@ enum reg_class
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#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
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#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
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#define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG)
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#define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG)
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#define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
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#define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG))
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#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
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#define REX_INT_REGNO_P(N) \
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IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
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#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
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#define GENERAL_REGNO_P(N) \
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@ -1454,22 +1472,9 @@ enum reg_class
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#define ANY_QI_REGNO_P(N) \
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(TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
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#define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
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#define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), AX_REG, SP_REG))
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#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
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#define REX_INT_REGNO_P(N) \
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IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
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#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
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#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
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#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
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#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
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#define X87_FLOAT_MODE_P(MODE) \
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(TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
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#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
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#define SSE_REGNO_P(N) \
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(IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
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@ -1482,32 +1487,30 @@ enum reg_class
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#define EXT_REX_SSE_REGNO_P(N) \
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IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
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#define SSE_REGNO(N) \
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((N) < 8 ? FIRST_SSE_REG + (N) \
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: (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
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: (FIRST_EXT_REX_SSE_REG + (N) - 16))
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#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
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#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
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#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
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#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
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#define SSE_FLOAT_MODE_P(MODE) \
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((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
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#define FMA4_VEC_FLOAT_MODE_P(MODE) \
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(TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
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|| (MODE) == V8SFmode || (MODE) == V4DFmode))
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#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
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#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
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#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG)
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#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
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#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
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#define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X)))
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#define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG)
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/* First floating point reg */
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#define FIRST_FLOAT_REG FIRST_STACK_REG
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#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
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#define SSE_REGNO(N) \
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((N) < 8 ? FIRST_SSE_REG + (N) \
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: (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
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: (FIRST_EXT_REX_SSE_REG + (N) - 16))
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/* The class value for index registers, and the one for base regs. */
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#define INDEX_REG_CLASS INDEX_REGS
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@ -324,9 +324,11 @@
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(ST5_REG 13)
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(ST6_REG 14)
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(ST7_REG 15)
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(ARGP_REG 16)
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(FLAGS_REG 17)
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(FPSR_REG 18)
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(FPCR_REG 19)
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(FRAME_REG 20)
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(XMM0_REG 21)
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(XMM1_REG 22)
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(XMM2_REG 23)
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@ -385,6 +387,9 @@
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(MASK7_REG 76)
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(BND0_REG 77)
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(BND1_REG 78)
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(BND2_REG 79)
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(BND3_REG 80)
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(FIRST_PSEUDO_REG 81)
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])
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;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
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