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RISC-V: Add testcases for form 4 of signed vector SAT_ADD

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Form 4:
  #define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)                     \
  void __attribute__((noinline))                                       \
  vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T sum;                                                         \
        bool overflow = __builtin_add_overflow (x, y, &sum);           \
        out[i] = !overflow ? sum : x < 0 ? MIN : MAX;                  \
      }                                                                \
  }

DEF_VEC_SAT_S_ADD_FMT_4 (int8_t, uint8_t, INT8_MIN, INT8_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2024-09-23 13:43:50 +08:00
parent fa546b6641
commit 03b469ee47
9 changed files with 126 additions and 0 deletions
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9
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c Normal file
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@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c Normal file
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@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c Normal file
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@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c Normal file
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@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

17
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
#include "../vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int8_t
#define T1 int8_t
#define T2 uint8_t
DEF_VEC_SAT_S_ADD_FMT_4_WRAP (T1, T2, INT8_MIN, INT8_MAX)
#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N)
#include "vec_sat_binary_vvv_run.h"

17
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
#include "../vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int16_t
#define T1 int16_t
#define T2 uint16_t
DEF_VEC_SAT_S_ADD_FMT_4_WRAP (T1, T2, INT16_MIN, INT16_MAX)
#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N)
#include "vec_sat_binary_vvv_run.h"

17
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
#include "../vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int32_t
#define T1 int32_t
#define T2 uint32_t
DEF_VEC_SAT_S_ADD_FMT_4_WRAP (T1, T2, INT32_MIN, INT32_MAX)
#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N)
#include "vec_sat_binary_vvv_run.h"

17
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99" } */
#include "../vec_sat_arith.h"
#include "vec_sat_data.h"
#define T int64_t
#define T1 int64_t
#define T2 uint64_t
DEF_VEC_SAT_S_ADD_FMT_4_WRAP (T1, T2, INT64_MIN, INT64_MAX)
#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N)
#include "vec_sat_binary_vvv_run.h"

22
gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
View file

@ -277,6 +277,23 @@ vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
#define DEF_VEC_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T sum; \
bool overflow = __builtin_add_overflow (x, y, &sum); \
out[i] = !overflow ? sum : x < 0 ? MIN : MAX; \
} \
}
#define DEF_VEC_SAT_S_ADD_FMT_4_WRAP(T, UT, MIN, MAX) \
DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)
#define RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_s_add_##T##_fmt_1(out, op_1, op_2, N)
#define RUN_VEC_SAT_S_ADD_FMT_1_WRAP(T, out, op_1, op_2, N) \
@ -292,6 +309,11 @@ vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
#define RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N)
#define RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N) \
vec_sat_s_add_##T##_fmt_4(out, op_1, op_2, N)
#define RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N)
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/