From 03848bd0e1cf3b39c535110db43e70bd355dc3e5 Mon Sep 17 00:00:00 2001
From: Bernd Schmidt <bernd.schmidt@analog.com>
Date: Tue, 11 Sep 2007 23:20:10 +0000
Subject: [PATCH] bfin.h (enum reg_class, [...]): Add P0REGS.

	* config/bfin/bfin.h (enum reg_class, REG_CLASS_CONTENTS,
	REG_CLASS_NAMES): Add P0REGS.
	(REGNO_REG_CLASS): Return it where appropriate.
	(REG_CLASS_FROM_CONSTRAINT): Add 'qA'.
	(CLASS_LIKELY_SPILLED_P): P0REGS is likely_spilled.
	* doc/md.texi (Blackfin family): Document 'q' constraints.

From-SVN: r128397
---
 gcc/ChangeLog          | 9 +++++++++
 gcc/config/bfin/bfin.h | 6 ++++++
 gcc/doc/md.texi        | 4 ++++
 3 files changed, 19 insertions(+)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 79d9e85d924..cd69a8cea82 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2007-09-12  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin/bfin.h (enum reg_class, REG_CLASS_CONTENTS,
+	REG_CLASS_NAMES): Add P0REGS.
+	(REGNO_REG_CLASS): Return it where appropriate.
+	(REG_CLASS_FROM_CONSTRAINT): Add 'qA'.
+	(CLASS_LIKELY_SPILLED_P): P0REGS is likely_spilled.
+	* doc/md.texi (Blackfin family): Document 'q' constraints.
+
 2007-09-11  Steve Kenton  <skenton@ou.edu
 
 	* pa/linux-unwind.h: Guard with inhibit_libc.
diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h
index 93c77c19e00..1d8e8dae9e0 100644
--- a/gcc/config/bfin/bfin.h
+++ b/gcc/config/bfin/bfin.h
@@ -464,6 +464,7 @@ enum reg_class
   D6REGS,
   D7REGS,
   DREGS,
+  P0REGS,
   FDPIC_REGS,
   FDPIC_FPTR_REGS,
   PREGS_CLOBBERED,
@@ -508,6 +509,7 @@ enum reg_class
    "D6REGS",		\
    "D7REGS",		\
    "DREGS",		\
+   "P0REGS",		\
    "FDPIC_REGS",	\
    "FDPIC_FPTR_REGS",	\
    "PREGS_CLOBBERED",	\
@@ -560,6 +562,7 @@ enum reg_class
     { 0x00000040,    0 },		/* D6REGS */   \
     { 0x00000080,    0 },		/* D7REGS */   \
     { 0x000000ff,    0 },		/* DREGS */   \
+    { 0x00000100,    0x000 },		/* P0REGS */   \
     { 0x00000800,    0x000 },		/* FDPIC_REGS */   \
     { 0x00000200,    0x000 },		/* FDPIC_FPTR_REGS */   \
     { 0x00004700,    0x800 },		/* PREGS_CLOBBERED */   \
@@ -636,6 +639,7 @@ enum reg_class
        : (STR)[1] == '5' ? D5REGS \
        : (STR)[1] == '6' ? D6REGS \
        : (STR)[1] == '7' ? D7REGS \
+       : (STR)[1] == 'A' ? P0REGS \
        : NO_REGS) : \
    NO_REGS)
 
@@ -653,6 +657,7 @@ enum reg_class
  : (REGNO) == REG_R5 ? D5REGS				\
  : (REGNO) == REG_R6 ? D6REGS				\
  : (REGNO) == REG_R7 ? D7REGS				\
+ : (REGNO) == REG_P0 ? P0REGS				\
  : (REGNO) < REG_I0 ? PREGS				\
  : (REGNO) == REG_ARGP ? PREGS				\
  : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS	\
@@ -675,6 +680,7 @@ enum reg_class
 #define CLASS_LIKELY_SPILLED_P(CLASS) \
     ((CLASS) == PREGS_CLOBBERED \
      || (CLASS) == PROLOGUE_REGS \
+     || (CLASS) == P0REGS \
      || (CLASS) == D0REGS \
      || (CLASS) == D1REGS \
      || (CLASS) == D2REGS \
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 553c58de081..e79444c5496 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2250,6 +2250,10 @@ D register
 @item z
 A call clobbered P register.
 
+@item q@var{n}
+A single register.  If @var{n} is in the range 0 to 7, the corresponding D
+register.  If it is @code{A}, then the register P0.
+
 @item D
 Even-numbered D register