i386: Cleanup ix86_expand_vecop_qihi{,2}
Some cleanups while looking at these two functions. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also reject ymm instructions for TARGET_PREFER_AVX128. Use generic gen_extend_insn to generate zero/sign extension instructions. Fix comments. (ix86_expand_vecop_qihi): Initialize interleave functions for MULT code only. Fix comments.
This commit is contained in:
Uros Bizjak
parent
6190a74ebe
commit
00fffa91f7
1 changed files with 37 additions and 27 deletions
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@ -23122,12 +23122,11 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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{
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machine_mode himode, qimode = GET_MODE (dest);
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rtx hop1, hop2, hdest;
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rtx (*gen_extend)(rtx, rtx);
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rtx (*gen_truncate)(rtx, rtx);
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bool uns_p = (code == ASHIFTRT) ? false : true;
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/* There's no V64HImode multiplication instruction. */
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if (qimode == E_V64QImode)
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/* There are no V64HImode instructions. */
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if (qimode == V64QImode)
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return false;
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/* vpmovwb only available under AVX512BW. */
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@ -23136,26 +23135,24 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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if ((qimode == V8QImode || qimode == V16QImode)
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&& !TARGET_AVX512VL)
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return false;
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/* Not generate zmm instruction when prefer 128/256 bit vector width. */
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if (qimode == V32QImode
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&& (TARGET_PREFER_AVX128 || TARGET_PREFER_AVX256))
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/* Do not generate ymm/zmm instructions when
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target prefers 128/256 bit vector width. */
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if ((qimode == V16QImode && TARGET_PREFER_AVX128)
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|| (qimode == V32QImode && TARGET_PREFER_AVX256))
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return false;
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switch (qimode)
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{
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case E_V8QImode:
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himode = V8HImode;
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gen_extend = uns_p ? gen_zero_extendv8qiv8hi2 : gen_extendv8qiv8hi2;
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gen_truncate = gen_truncv8hiv8qi2;
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break;
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case E_V16QImode:
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himode = V16HImode;
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gen_extend = uns_p ? gen_zero_extendv16qiv16hi2 : gen_extendv16qiv16hi2;
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gen_truncate = gen_truncv16hiv16qi2;
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break;
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case E_V32QImode:
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himode = V32HImode;
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gen_extend = uns_p ? gen_zero_extendv32qiv32hi2 : gen_extendv32qiv32hi2;
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gen_truncate = gen_truncv32hiv32qi2;
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break;
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default:
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@ -23165,8 +23162,8 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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hop1 = gen_reg_rtx (himode);
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hop2 = gen_reg_rtx (himode);
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hdest = gen_reg_rtx (himode);
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emit_insn (gen_extend (hop1, op1));
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emit_insn (gen_extend (hop2, op2));
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emit_insn (gen_extend_insn (hop1, op1, himode, qimode, uns_p));
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emit_insn (gen_extend_insn (hop2, op2, himode, qimode, uns_p));
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emit_insn (gen_rtx_SET (hdest, simplify_gen_binary (code, himode,
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hop1, hop2)));
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emit_insn (gen_truncate (dest, hdest));
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@ -23285,8 +23282,9 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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rtx (*gen_ih) (rtx, rtx, rtx);
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rtx op1_l, op1_h, op2_l, op2_h, res_l, res_h;
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struct expand_vec_perm_d d;
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bool ok, full_interleave;
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bool uns_p = false;
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bool full_interleave = true;
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bool uns_p = true;
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bool ok;
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int i;
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if (CONST_INT_P (op2)
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@ -23303,18 +23301,12 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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{
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case E_V16QImode:
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himode = V8HImode;
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gen_il = gen_vec_interleave_lowv16qi;
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gen_ih = gen_vec_interleave_highv16qi;
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break;
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case E_V32QImode:
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himode = V16HImode;
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gen_il = gen_avx2_interleave_lowv32qi;
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gen_ih = gen_avx2_interleave_highv32qi;
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break;
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case E_V64QImode:
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himode = V32HImode;
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gen_il = gen_avx512bw_interleave_lowv64qi;
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gen_ih = gen_avx512bw_interleave_highv64qi;
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break;
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default:
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gcc_unreachable ();
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@ -23327,6 +23319,26 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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each word. We don't care what goes into the high byte of each word.
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Rather than trying to get zero in there, most convenient is to let
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it be a copy of the low byte. */
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switch (qimode)
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{
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case E_V16QImode:
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gen_il = gen_vec_interleave_lowv16qi;
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gen_ih = gen_vec_interleave_highv16qi;
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break;
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case E_V32QImode:
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gen_il = gen_avx2_interleave_lowv32qi;
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gen_ih = gen_avx2_interleave_highv32qi;
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full_interleave = false;
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break;
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case E_V64QImode:
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gen_il = gen_avx512bw_interleave_lowv64qi;
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gen_ih = gen_avx512bw_interleave_highv64qi;
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full_interleave = false;
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break;
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default:
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gcc_unreachable ();
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}
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op2_l = gen_reg_rtx (qimode);
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op2_h = gen_reg_rtx (qimode);
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emit_insn (gen_il (op2_l, op2, op2));
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@ -23336,14 +23348,13 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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op1_h = gen_reg_rtx (qimode);
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emit_insn (gen_il (op1_l, op1, op1));
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emit_insn (gen_ih (op1_h, op1, op1));
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full_interleave = qimode == V16QImode;
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break;
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case ASHIFTRT:
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uns_p = false;
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/* FALLTHRU */
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case ASHIFT:
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case LSHIFTRT:
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uns_p = true;
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/* FALLTHRU */
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case ASHIFTRT:
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op1_l = gen_reg_rtx (himode);
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op1_h = gen_reg_rtx (himode);
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ix86_expand_sse_unpack (op1_l, op1, uns_p, false);
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@ -23360,16 +23371,15 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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else
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op2_l = op2_h = op2;
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full_interleave = true;
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break;
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default:
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gcc_unreachable ();
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}
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/* Perform vashr/vlshr/vashl. */
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if (code != MULT
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&& GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT)
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{
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/* Expand vashr/vlshr/vashl. */
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res_l = gen_reg_rtx (himode);
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res_h = gen_reg_rtx (himode);
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emit_insn (gen_rtx_SET (res_l,
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@ -23379,9 +23389,9 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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simplify_gen_binary (code, himode,
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op1_h, op2_h)));
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}
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/* Performance mult/ashr/lshr/ashl. */
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else
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{
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/* Expand mult/ashr/lshr/ashl. */
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res_l = expand_simple_binop (himode, code, op1_l, op2_l, NULL_RTX,
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1, OPTAB_DIRECT);
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res_h = expand_simple_binop (himode, code, op1_h, op2_h, NULL_RTX,
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@ -23401,7 +23411,7 @@ ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
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if (full_interleave)
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{
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/* For SSE2, we used an full interleave, so the desired
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/* We used the full interleave, the desired
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results are in the even elements. */
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for (i = 0; i < d.nelt; ++i)
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d.perm[i] = i * 2;
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