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[AArch64, 4/6] Reimplement frsqrts intrinsics

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* config/aarch64/aarch64-builtins.def (rsqrts): New builtins for modes
	VALLF.
	* config/aarch64/aarch64-simd.md (aarch64_rsqrts_<mode>3): Rename to
	"aarch64_rsqrts<mode>".
	* config/aarch64/aarch64.c (get_rsqrts_type): Update gen* name.
	* config/aarch64/arm_neon.h (vrsqrtss_f32): Remove inline assembly.  Use
	builtin.
	(vrsqrtsd_f64): Likewise.
	(vrsqrts_f32): Likewise.
	(vrsqrts_f64): Likewise.
	(vrsqrtsq_f32): Likewise.
	(vrsqrtsq_f64): Likewise.

From-SVN: r237203
This commit is contained in:
Jiong Wang 2016-06-08 10:14:30 +00:00 • committed by Jiong Wang
parent 2a82343319
commit 00ea75d4e2
5 changed files with 63 additions and 61 deletions
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15
gcc/ChangeLog
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@ -1,3 +1,18 @@
2016-06-08 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-builtins.def (rsqrts): New builtins for modes
VALLF.
* config/aarch64/aarch64-simd.md (aarch64_rsqrts_<mode>3): Rename to
"aarch64_rsqrts<mode>".
* config/aarch64/aarch64.c (get_rsqrts_type): Update gen* name.
* config/aarch64/arm_neon.h (vrsqrtss_f32): Remove inline assembly. Use
builtin.
(vrsqrtsd_f64): Likewise.
(vrsqrts_f32): Likewise.
(vrsqrts_f64): Likewise.
(vrsqrtsq_f32): Likewise.
(vrsqrtsq_f64): Likewise.
2016-06-08 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-builtins.def (rsqrte): New builtins for modes

3
gcc/config/aarch64/aarch64-simd-builtins.def
View file

@ -454,3 +454,6 @@
/* Implemented by aarch64_rsqrte<mode>. */
BUILTIN_VALLF (UNOP, rsqrte, 0)
/* Implemented by aarch64_rsqrts<mode>. */
BUILTIN_VALLF (BINOP, rsqrts, 0)

2
gcc/config/aarch64/aarch64-simd.md
View file

@ -390,7 +390,7 @@
"frsqrte\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
[(set_attr "type" "neon_fp_rsqrte_<Vetype><q>")])
(define_insn "aarch64_rsqrts_<mode>3"
(define_insn "aarch64_rsqrts<mode>"
[(set (match_operand:VALLF 0 "register_operand" "=w")
(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
(match_operand:VALLF 2 "register_operand" "w")]

10
gcc/config/aarch64/aarch64.c
View file

@ -7368,11 +7368,11 @@ get_rsqrts_type (machine_mode mode)
{
switch (mode)
{
case DFmode: return gen_aarch64_rsqrts_df3;
case SFmode: return gen_aarch64_rsqrts_sf3;
case V2DFmode: return gen_aarch64_rsqrts_v2df3;
case V2SFmode: return gen_aarch64_rsqrts_v2sf3;
case V4SFmode: return gen_aarch64_rsqrts_v4sf3;
case DFmode: return gen_aarch64_rsqrtsdf;
case SFmode: return gen_aarch64_rsqrtssf;
case V2DFmode: return gen_aarch64_rsqrtsv2df;
case V2SFmode: return gen_aarch64_rsqrtsv2sf;
case V4SFmode: return gen_aarch64_rsqrtsv4sf;
default: gcc_unreachable ();
}
}

94
gcc/config/aarch64/arm_neon.h
View file

@ -9185,61 +9185,6 @@ vrsqrteq_u32 (uint32x4_t a)
return result;
}
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vrsqrts_f32 (float32x2_t a, float32x2_t b)
{
float32x2_t result;
__asm__ ("frsqrts %0.2s,%1.2s,%2.2s"
: "=w"(result)
: "w"(a), "w"(b)
: /* No clobbers */);
return result;
}
__extension__ static __inline float64_t __attribute__ ((__always_inline__))
vrsqrtsd_f64 (float64_t a, float64_t b)
{
float64_t result;
__asm__ ("frsqrts %d0,%d1,%d2"
: "=w"(result)
: "w"(a), "w"(b)
: /* No clobbers */);
return result;
}
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrsqrtsq_f32 (float32x4_t a, float32x4_t b)
{
float32x4_t result;
__asm__ ("frsqrts %0.4s,%1.4s,%2.4s"
: "=w"(result)
: "w"(a), "w"(b)
: /* No clobbers */);
return result;
}
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vrsqrtsq_f64 (float64x2_t a, float64x2_t b)
{
float64x2_t result;
__asm__ ("frsqrts %0.2d,%1.2d,%2.2d"
: "=w"(result)
: "w"(a), "w"(b)
: /* No clobbers */);
return result;
}
__extension__ static __inline float32_t __attribute__ ((__always_inline__))
vrsqrtss_f32 (float32_t a, float32_t b)
{
float32_t result;
__asm__ ("frsqrts %s0,%s1,%s2"
: "=w"(result)
: "w"(a), "w"(b)
: /* No clobbers */);
return result;
}
#define vshrn_high_n_s16(a, b, c) \
__extension__ \
({ \
@ -21476,6 +21421,45 @@ vrsqrteq_f64 (float64x2_t __a)
return __builtin_aarch64_rsqrtev2df (__a);
}
/* vrsqrts. */
__extension__ static __inline float32_t __attribute__ ((__always_inline__))
vrsqrtss_f32 (float32_t __a, float32_t __b)
{
return __builtin_aarch64_rsqrtssf (__a, __b);
}
__extension__ static __inline float64_t __attribute__ ((__always_inline__))
vrsqrtsd_f64 (float64_t __a, float64_t __b)
{
return __builtin_aarch64_rsqrtsdf (__a, __b);
}
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vrsqrts_f32 (float32x2_t __a, float32x2_t __b)
{
return __builtin_aarch64_rsqrtsv2sf (__a, __b);
}
__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
vrsqrts_f64 (float64x1_t __a, float64x1_t __b)
{
return (float64x1_t) {vrsqrtsd_f64 (vget_lane_f64 (__a, 0),
vget_lane_f64 (__b, 0))};
}
__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
vrsqrtsq_f32 (float32x4_t __a, float32x4_t __b)
{
return __builtin_aarch64_rsqrtsv4sf (__a, __b);
}
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vrsqrtsq_f64 (float64x2_t __a, float64x2_t __b)
{
return __builtin_aarch64_rsqrtsv2df (__a, __b);
}
/* vrsra */
__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))