h8300.c (ok_for_bclr): Take a HOST_WIDE_INT.
* config/h8300/h8300.c (ok_for_bclr): Take a HOST_WIDE_INT.
(small_power_of_two): Likewise; use exact_log2.
(adds_subs_operand, one_insn_adds_subs_operand): Remove.
(output_adds_subs): Remove.
(two_insn_adds_subs_operand): New.
(split_adds_subs): New.
* config/h8300/h8300-protos.h: Update.
* config/h8300/h8300.h (CONST_OK_FOR_J): Cast to uns HOST_WIDE_INT.
(CONST_OK_FOR_L): Match strict adds operands.
(CONST_OK_FOR_N): Match struct subs operands.
* config/h8300/h8300.md (adds_subs insns): Remove.
(addhi patterns): Output adds/subs directly.
(addsi_h8300h): Likewise.
(addhi/addsi splitters): New. Decompose two_insn_adds_subs_operand.
From-SVN: r33985
This commit is contained in:
Richard Henderson
Richard Henderson
parent
15dad1d908
commit
009ac3d324
5 changed files with 134 additions and 193 deletions
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@ -1,3 +1,20 @@
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2000-05-18 Richard Henderson <rth@cygnus.com>
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* config/h8300/h8300.c (ok_for_bclr): Take a HOST_WIDE_INT.
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(small_power_of_two): Likewise; use exact_log2.
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(adds_subs_operand, one_insn_adds_subs_operand): Remove.
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(output_adds_subs): Remove.
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(two_insn_adds_subs_operand): New.
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(split_adds_subs): New.
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* config/h8300/h8300-protos.h: Update.
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* config/h8300/h8300.h (CONST_OK_FOR_J): Cast to uns HOST_WIDE_INT.
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(CONST_OK_FOR_L): Match strict adds operands.
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(CONST_OK_FOR_N): Match struct subs operands.
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* config/h8300/h8300.md (adds_subs insns): Remove.
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(addhi patterns): Output adds/subs directly.
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(addsi_h8300h): Likewise.
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(addhi/addsi splitters): New. Decompose two_insn_adds_subs_operand.
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2000-05-18 Zack Weinberg <zack@wolery.cumb.org>
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* cppexp.c (parse_assertion): New.
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@ -36,14 +36,14 @@ extern void notice_update_cc PARAMS ((rtx, rtx));
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extern int expand_a_shift PARAMS ((enum machine_mode, int, rtx[]));
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extern int fix_bit_operand PARAMS ((rtx *, int, enum rtx_code));
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extern int h8300_adjust_insn_length PARAMS ((rtx, int));
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extern void split_adds_subs PARAMS ((enum machine_mode, rtx[]));
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extern int general_operand_src PARAMS ((rtx, enum machine_mode));
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extern int general_operand_dst PARAMS ((rtx, enum machine_mode));
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extern int o_operand PARAMS ((rtx, enum machine_mode));
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extern int p_operand PARAMS ((rtx, enum machine_mode));
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extern int call_insn_operand PARAMS ((rtx, enum machine_mode));
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extern int adds_subs_operand PARAMS ((rtx, enum machine_mode));
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extern int one_insn_adds_subs_operand PARAMS ((rtx, enum machine_mode));
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extern int two_insn_adds_subs_operand PARAMS ((rtx, enum machine_mode));
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extern int small_call_insn_operand PARAMS ((rtx, enum machine_mode));
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extern int jump_address_operand PARAMS ((rtx, enum machine_mode));
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extern int bit_operand PARAMS ((rtx, enum machine_mode));
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@ -70,6 +70,6 @@ extern void function_prologue PARAMS ((FILE *, int));
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extern void function_epilogue PARAMS ((FILE *, int));
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extern void asm_file_start PARAMS ((FILE *));
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extern void asm_file_end PARAMS ((FILE *));
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extern int ok_for_bclr PARAMS ((int));
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extern int small_power_of_two PARAMS ((int));
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extern int ok_for_bclr PARAMS ((HOST_WIDE_INT));
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extern int small_power_of_two PARAMS ((HOST_WIDE_INT));
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extern int initial_offset PARAMS ((int, int));
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@ -542,29 +542,10 @@ asm_file_end (file)
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int
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small_power_of_two (value)
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int value;
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HOST_WIDE_INT value;
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{
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switch (value)
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{
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case 1:
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case 2:
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case 4:
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case 8:
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case 16:
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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case 1024:
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case 2048:
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case 4096:
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case 8192:
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case 16384:
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case 32768:
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return 1;
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}
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return 0;
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int power = exact_log2 (value);
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return power >= 0 && power <= 15;
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}
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/* Return true if VALUE is a valid constant for constraint 'O', which
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@ -573,7 +554,7 @@ small_power_of_two (value)
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int
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ok_for_bclr (value)
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int value;
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HOST_WIDE_INT value;
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{
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return small_power_of_two ((~value) & 0xff);
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}
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@ -645,107 +626,92 @@ call_insn_operand (op, mode)
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}
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int
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adds_subs_operand (op, mode)
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two_insn_adds_subs_operand (op, mode)
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rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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if (GET_CODE (op) == CONST_INT)
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{
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if (INTVAL (op) <= 4 && INTVAL (op) >= 0)
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return 1;
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if (INTVAL (op) >= -4 && INTVAL (op) <= 0)
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return 1;
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if ((TARGET_H8300H || TARGET_H8300S)
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&& INTVAL (op) != 7
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&& (INTVAL (op) <= 8 && INTVAL (op) >= 0))
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return 1;
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if ((TARGET_H8300H || TARGET_H8300S)
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&& INTVAL (op) != -7
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&& (INTVAL (op) >= -8 && INTVAL (op) <= 0))
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return 1;
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HOST_WIDE_INT value = INTVAL (op);
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if (TARGET_H8300H || TARGET_H8300S)
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{
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if (value >= -8 && value < -4 && value != -7)
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return 1;
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if (value > 4 && value <= 8 && value != 7)
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return 1;
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}
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else
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{
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if (value == -4 || value == -3 || value == 3 || value == 4)
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return 1;
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}
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}
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return 0;
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}
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/* Return nonzero if op is an adds/subs operand which only requires
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one insn to implement. It is assumed that OP is already an adds/subs
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operand. */
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int
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one_insn_adds_subs_operand (op, mode)
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rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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int val = INTVAL (op);
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/* Split an add of a small constant into two adds/subs insns. */
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if (val == 1 || val == -1
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|| val == 2 || val == -2
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|| ((TARGET_H8300H || TARGET_H8300S)
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&& (val == 4 || val == -4)))
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return 1;
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return 0;
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}
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const char *
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output_adds_subs (operands)
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void
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split_adds_subs (mode, operands)
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enum machine_mode mode;
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rtx *operands;
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{
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int val = INTVAL (operands[2]);
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HOST_WIDE_INT val = INTVAL (operands[1]);
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rtx reg = operands[0];
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rtx tmp;
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/* First get the value into the range -4..4 inclusive.
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The only way it can be out of this range is when TARGET_H8300H
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or TARGET_H8300S is true, thus it is safe to use adds #4 and subs #4. */
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if (val > 4)
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/* Take care of +/- 4 for H8300H and H8300S. */
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if (TARGET_H8300H || TARGET_H8300S)
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{
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output_asm_insn ("adds #4,%A0", operands);
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val -= 4;
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/* Get the value in range of +/- 4. */
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if (val > 4)
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{
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tmp = gen_rtx_PLUS (mode, reg, GEN_INT (4));
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emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
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val -= 4;
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}
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else if (val < -4)
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{
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tmp = gen_rtx_PLUS (mode, reg, GEN_INT (-4));
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emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
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val += 4;
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}
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if (val == 4 || val == -4)
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{
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tmp = gen_rtx_PLUS (mode, reg, GEN_INT (val));
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emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
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return;
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}
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}
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if (val < -4)
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{
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output_asm_insn ("subs #4,%A0", operands);
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val += 4;
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}
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/* Handle case were val == 4 or val == -4 and we're compiling
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for TARGET_H8300H or TARGET_H8300S. */
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if ((TARGET_H8300H || TARGET_H8300S)
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&& val == 4)
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return "adds #4,%A0";
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if ((TARGET_H8300H || TARGET_H8300S)
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&& val == -4)
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return "subs #4,%A0";
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/* Get the value in range of +/- 2. */
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if (val > 2)
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{
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output_asm_insn ("adds #2,%A0", operands);
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tmp = gen_rtx_PLUS (mode, reg, GEN_INT (2));
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emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
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val -= 2;
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}
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if (val < -2)
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else if (val < -2)
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{
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output_asm_insn ("subs #2,%A0", operands);
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tmp = gen_rtx_PLUS (mode, reg, GEN_INT (-2));
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emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
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val += 2;
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}
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/* val should be one or two now. */
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if (val == 2)
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return "adds #2,%A0";
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if (val == -2)
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return "subs #2,%A0";
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/* val should be one now. */
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if (val == 1)
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return "adds #1,%A0";
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if (val == -1)
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return "subs #1,%A0";
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/* If not optimizing, we might be asked to add 0. */
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if (val == 0)
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return "";
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return;
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/* We should have one or two now. */
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if (val >= -2 && val <= 2)
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{
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tmp = gen_rtx_PLUS (mode, reg, GEN_INT (val));
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emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
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return;
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}
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/* In theory, this can't happen. */
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abort ();
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@ -399,11 +399,17 @@ enum reg_class {
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Return 1 if VALUE is in the range specified by C. */
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#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
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#define CONST_OK_FOR_J(VALUE) ((unsigned) (VALUE) < 256)
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#define CONST_OK_FOR_K(VALUE) (((VALUE) == 1) || (VALUE) == 2)
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#define CONST_OK_FOR_L(VALUE) (((VALUE) == -1) || (VALUE) == -2)
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#define CONST_OK_FOR_M(VALUE) (((VALUE) == 3) || (VALUE) == 4)
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#define CONST_OK_FOR_N(VALUE) (((VALUE) == -3) || (VALUE) == -4)
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#define CONST_OK_FOR_J(VALUE) ((unsigned HOST_WIDE_INT) (VALUE) < 256)
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#define CONST_OK_FOR_K(VALUE) ((VALUE) == 1 || (VALUE) == 2)
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#define CONST_OK_FOR_L(VALUE) \
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(TARGET_H8300H || TARGET_H8300S \
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? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 4 \
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: (VALUE) == 1 || (VALUE) == 2)
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#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3 || (VALUE) == 4)
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#define CONST_OK_FOR_N(VALUE) \
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(TARGET_H8300H || TARGET_H8300S \
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? (VALUE) == -1 || (VALUE) == -2 || (VALUE) == -4 \
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: (VALUE) == -1 || (VALUE) == -2)
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#define CONST_OK_FOR_O(VALUE) (ok_for_bclr (VALUE))
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#define CONST_OK_FOR_P(VALUE) (small_power_of_two (VALUE))
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@ -415,7 +421,7 @@ enum reg_class {
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(C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
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(C) == 'N' ? CONST_OK_FOR_N (VALUE) : \
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(C) == 'O' ? CONST_OK_FOR_O (VALUE) : \
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(C) == 'P' ? CONST_OK_FOR_P(VALUE) : \
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(C) == 'P' ? CONST_OK_FOR_P (VALUE) : \
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0)
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/* Similar, but for floating constants, and defining letters G and H.
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@ -614,43 +614,40 @@
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""
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"")
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;; Specialized version using adds/subs. This must come before
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;; the more general patterns below.
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(plus:HI (match_operand:HI 1 "register_operand" "%0")
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(match_operand:HI 2 "adds_subs_operand" "n")))]
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""
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"* return output_adds_subs (operands);"
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[(set_attr "cc" "none_0hit")
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(set (attr "length")
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(if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
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(const_int 0))
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(const_int 2)
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(const_int 4)))])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=&r,r,&r")
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(plus:HI (match_operand:HI 1 "register_operand" "%0,0,g")
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(match_operand:HI 2 "nonmemory_operand" "n,r,r")))]
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
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(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
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(match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
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"TARGET_H8300"
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"@
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adds %2,%A0
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subs %2,%A0
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add.b %s2,%s0\;addx %t2,%t0
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add.w %T2,%T0
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mov.w %T1,%T0\;add.w %T2,%T0"
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[(set_attr "length" "4,2,6")
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(set_attr "cc" "clobber,set_zn,set_zn")])
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[(set_attr "length" "2,2,4,2,6")
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(set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(plus:HI (match_operand:HI 1 "register_operand" "%0,0")
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(match_operand:HI 2 "nonmemory_operand" "n,r")))]
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
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(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
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(match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
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"TARGET_H8300H || TARGET_H8300S"
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"@
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adds %2,%A0
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subs %2,%A0
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add.w %T2,%T0
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add.w %T2,%T0"
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[(set_attr "length" "4,2")
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(set_attr "cc" "set_zn,set_zn")])
|
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[(set_attr "length" "2,2,4,2")
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(set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
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|
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(define_split
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[(set (match_operand:HI 0 "register_operand" "")
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(plus:HI (match_dup 0)
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(match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
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""
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||||
[(const_int 0)]
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"split_adds_subs (HImode, operands); DONE;")
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|
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(define_expand "addsi3"
|
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[(set (match_operand:SI 0 "register_operand" "")
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|
|
@ -659,21 +656,6 @@
|
|||
""
|
||||
"")
|
||||
|
||||
;; Specialized version using adds/subs. This must come before
|
||||
;; the more general patterns below.
|
||||
(define_insn ""
|
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[(set (match_operand:SI 0 "register_operand" "=r")
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||||
(plus:SI (match_operand:SI 1 "register_operand" "%0")
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||||
(match_operand:SI 2 "adds_subs_operand" "n")))]
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
"* return output_adds_subs (operands);"
|
||||
[(set_attr "cc" "none_0hit")
|
||||
(set (attr "length")
|
||||
(if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
|
||||
(const_int 0))
|
||||
(const_int 2)
|
||||
(const_int 4)))])
|
||||
|
||||
(define_insn "addsi_h8300"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,&r")
|
||||
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
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||||
|
|
@ -687,15 +669,25 @@
|
|||
(set_attr "cc" "clobber")])
|
||||
|
||||
(define_insn "addsi_h8300h"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(plus:SI (match_operand:SI 1 "register_operand" "%0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "i,r")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
||||
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
|
||||
(match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
"@
|
||||
adds %2,%A0
|
||||
subs %2,%A0
|
||||
add.l %S2,%S0
|
||||
add.l %S2,%S0"
|
||||
[(set_attr "length" "6,2")
|
||||
(set_attr "cc" "set_zn,set_zn")])
|
||||
[(set_attr "length" "2,2,6,2")
|
||||
(set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(plus:SI (match_dup 0)
|
||||
(match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
[(const_int 0)]
|
||||
"split_adds_subs (SImode, operands); DONE;")
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; SUBTRACT INSTRUCTIONS
|
||||
|
|
@ -719,26 +711,6 @@
|
|||
""
|
||||
"")
|
||||
|
||||
;; Specialized version using adds/subs. This must come before
|
||||
;; the more general patterns below. This may not be needed
|
||||
;; due to instruction canonicalization.
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(minus:HI (match_operand:HI 1 "register_operand" "r")
|
||||
(match_operand:HI 2 "adds_subs_operand" "n")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
operands[2] = GEN_INT (-INTVAL (operands[2]));
|
||||
return output_adds_subs (operands);
|
||||
}"
|
||||
[(set_attr "cc" "none_0hit")
|
||||
(set (attr "length")
|
||||
(if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
|
||||
(const_int 0))
|
||||
(const_int 2)
|
||||
(const_int 4)))])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,&r")
|
||||
(minus:HI (match_operand:HI 1 "general_operand" "0,0")
|
||||
|
|
@ -777,26 +749,6 @@
|
|||
[(set_attr "length" "6")
|
||||
(set_attr "cc" "clobber")])
|
||||
|
||||
;; Specialized version using adds/subs. This must come before
|
||||
;; the more general patterns below. This may not be needed
|
||||
;; due to instruction canonicalization.
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(minus:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "adds_subs_operand" "n")))]
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
"*
|
||||
{
|
||||
operands[2] = GEN_INT (-INTVAL (operands[2]));
|
||||
return output_adds_subs (operands);
|
||||
}"
|
||||
[(set_attr "cc" "none_0hit")
|
||||
(set (attr "length")
|
||||
(if_then_else (ne (match_operand:HI 2 "one_insn_adds_subs_operand" "")
|
||||
(const_int 0))
|
||||
(const_int 2)
|
||||
(const_int 4)))])
|
||||
|
||||
(define_insn "subsi3_h8300h"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(minus:SI (match_operand:SI 1 "general_operand" "0,0")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue