2025-01-02 11:59:57 +01:00
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/* Copyright (C) 1994-2025 Free Software Foundation, Inc.
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1994-09-09 23:40:17 +00:00
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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2009-04-09 17:00:19 +02:00
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Free Software Foundation; either version 3, or (at your option) any
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1994-09-09 23:40:17 +00:00
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later version.
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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2009-04-09 17:00:19 +02:00
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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1994-09-09 23:40:17 +00:00
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2003-06-17 19:19:16 +00:00
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!! libgcc routines for the Renesas / SuperH SH CPUs.
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1994-09-09 23:40:17 +00:00
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!! Contributed by Steve Chamberlain.
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!! sac@cygnus.com
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1995-04-27 18:08:43 -07:00
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!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
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!! recoded in assembly by Toshiyasu Morita
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!! tm@netcom.com
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1994-09-09 23:40:17 +00:00
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2009-04-17 22:20:40 +00:00
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#if defined(__ELF__) && defined(__linux__)
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.section .note.GNU-stack,"",%progbits
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.previous
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#endif
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1998-10-02 08:22:31 +00:00
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/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
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ELF local label prefixes by J"orn Rennecke
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amylaar@cygnus.com */
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2006-04-12 20:09:41 +00:00
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#include "lib1funcs.h"
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Introduce sh2a support.
2004-07-29 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Build multilibs for sh2a and sh2a-single by
default.
* config/sh/sh.h (SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Define by
default. Split their tests out of the corresponding SH4
multilibs.
* config/sh/t-sh (MULTILIB_MATCHES): Don't ever use SH4 or SH4a
multilibs for SH2a.
2004-07-28 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Handle sh2a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh2a command line flags.
* config/sh/t-mlib-sh2a: New.
* config/sh/t-mlib-sh2a-nofpu: New.
* config/sh/t-mlib-sh2a-single: New.
* config/sh/t-mlib-sh2a-single-only: New.
2004-07-09 Nick Clifton <nickc@redhat.com>
Issue 43400
* config/sh/sh.h (DRIVER_SELF_SPECS): Issue an error message if
-ml and -m2a are used together.
2004-03-23 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (sh_builtin_saveregs): Use the double code only
when we have a double-sized FPU.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/lib1funcs.asm (set_fpscr): Don't build if __SH2A_NOFPU__
is set.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Add cases for -msh2a-nofpu,
-msh2a-single and -msh2a-single-only
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/crt1.asm: Don't generate FPU instructions if __SH2A_NOFPU__
is set.
2004-02-20 DJ Delorie <dj@delorie.com>
* config/sh/sh.md (movsf_i, movsf_ie, movsf, ble, bge): Disable for sh2a-nofpu.
2004-02-20 Fred Fish <fnf@redhat.com>,
Corinna Vinschen <vinschen@redhat.com>
* config/sh/t-sh (MULTILIB_OPTIONS): Add 2a-nofpu.
(MULTILIB_EXCEPTIONS): Don't build littel-endian on sh2a.
2004-02-18 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (broken_move): Add support for movi20.
* config/sh/sh.h: Likewise.
(SHIFT_COUNT_TRUNCATED): Set for sh2a.
* config/sh/sh.md (udivsi3_sh2a): New.
(udivsi3): Call it.
(divsi3_sh2a): New.
(divsi3): Call it.
(mul_r): New.
(ashlsi3_sh2a): New.
(ashrsi3_sh2a): New.
(lshrsi3_sh2a): New.
(movsi_i): Disable for sh2a.
(movsi_ie): Add movi20.
(movsf_i, movsf_ie, movsf, ble, untyped_call): Explicitly enable
sh2a, for -m2a-nofpu mode.
2004-02-13 DJ Delorie <dj@redhat.com>
* config/sh/lib1funcs.asm: Handle double vs single better.
* config/sh/sh.h: Likewise.
2004-02-09 DJ Delorie <dj@redhat.com>
* config/sh/crt1.asm: Add support for sh2a.
* config/sh/elf.h: Likewise.
* config/sh/lib1funcs.asm: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/t-sh: Likewise.
From-SVN: r85286
2004-07-29 06:10:03 +00:00
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2007-04-25 08:03:55 +00:00
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/* t-vxworks needs to build both PIC and non-PIC versions of libgcc,
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so it is more convenient to define NO_FPSCR_VALUES here than to
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define it on the command line. */
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#if defined __vxworks && defined __PIC__
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#define NO_FPSCR_VALUES
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#endif
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1994-09-09 23:40:17 +00:00
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#ifdef L_ashiftrt
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2000-08-16 21:17:40 +00:00
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.global GLOBAL(ashiftrt_r4_0)
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.global GLOBAL(ashiftrt_r4_1)
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.global GLOBAL(ashiftrt_r4_2)
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.global GLOBAL(ashiftrt_r4_3)
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.global GLOBAL(ashiftrt_r4_4)
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.global GLOBAL(ashiftrt_r4_5)
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.global GLOBAL(ashiftrt_r4_6)
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.global GLOBAL(ashiftrt_r4_7)
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.global GLOBAL(ashiftrt_r4_8)
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.global GLOBAL(ashiftrt_r4_9)
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.global GLOBAL(ashiftrt_r4_10)
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.global GLOBAL(ashiftrt_r4_11)
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.global GLOBAL(ashiftrt_r4_12)
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.global GLOBAL(ashiftrt_r4_13)
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.global GLOBAL(ashiftrt_r4_14)
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.global GLOBAL(ashiftrt_r4_15)
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.global GLOBAL(ashiftrt_r4_16)
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.global GLOBAL(ashiftrt_r4_17)
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.global GLOBAL(ashiftrt_r4_18)
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.global GLOBAL(ashiftrt_r4_19)
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.global GLOBAL(ashiftrt_r4_20)
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.global GLOBAL(ashiftrt_r4_21)
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.global GLOBAL(ashiftrt_r4_22)
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.global GLOBAL(ashiftrt_r4_23)
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.global GLOBAL(ashiftrt_r4_24)
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.global GLOBAL(ashiftrt_r4_25)
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.global GLOBAL(ashiftrt_r4_26)
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.global GLOBAL(ashiftrt_r4_27)
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.global GLOBAL(ashiftrt_r4_28)
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.global GLOBAL(ashiftrt_r4_29)
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.global GLOBAL(ashiftrt_r4_30)
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.global GLOBAL(ashiftrt_r4_31)
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.global GLOBAL(ashiftrt_r4_32)
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1994-09-09 23:40:17 +00:00
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_0))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_1))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_2))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_3))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_4))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_5))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_6))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_7))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_8))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_9))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_10))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_11))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_12))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_13))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_14))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_15))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_16))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_17))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_18))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_19))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_20))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_21))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_22))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_23))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_24))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_25))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_26))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_27))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_28))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_29))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_30))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_31))
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HIDDEN_FUNC(GLOBAL(ashiftrt_r4_32))
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2002-12-16 18:23:00 +00:00
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1995-04-27 18:08:43 -07:00
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.align 1
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_32):
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GLOBAL(ashiftrt_r4_31):
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1995-04-27 18:08:43 -07:00
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rotcl r4
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rts
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subc r4,r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_30):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_29):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_28):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_27):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_26):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_25):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_24):
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1995-04-27 18:08:43 -07:00
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shlr16 r4
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shlr8 r4
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rts
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exts.b r4,r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_23):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashiftrt_r4_22):
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1994-09-09 23:40:17 +00:00
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shar r4
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2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_21):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_20):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_19):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_18):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_17):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_16):
|
1995-04-27 18:08:43 -07:00
|
|
|
shlr16 r4
|
|
|
|
|
rts
|
|
|
|
|
exts.w r4,r4
|
|
|
|
|
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_15):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_14):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_13):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_12):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_11):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_10):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_9):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_8):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_7):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_6):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_5):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_4):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_3):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_2):
|
1994-09-09 23:40:17 +00:00
|
|
|
shar r4
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_1):
|
1994-09-09 23:40:17 +00:00
|
|
|
rts
|
|
|
|
|
shar r4
|
|
|
|
|
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashiftrt_r4_0):
|
1994-09-09 23:40:17 +00:00
|
|
|
rts
|
1994-12-16 17:13:41 -08:00
|
|
|
nop
|
2002-12-16 18:23:00 +00:00
|
|
|
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_0))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_1))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_2))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_3))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_4))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_5))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_6))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_7))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_8))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_9))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_10))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_11))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_12))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_13))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_14))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_15))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_16))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_17))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_18))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_19))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_20))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_21))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_22))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_23))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_24))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_25))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_26))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_27))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_28))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_29))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_30))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_31))
|
|
|
|
|
ENDFUNC(GLOBAL(ashiftrt_r4_32))
|
1994-09-09 23:40:17 +00:00
|
|
|
#endif
|
|
|
|
|
|
1995-04-27 18:08:43 -07:00
|
|
|
#ifdef L_ashiftrt_n
|
|
|
|
|
|
|
|
|
|
!
|
2000-08-16 21:17:40 +00:00
|
|
|
! GLOBAL(ashrsi3)
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Entry:
|
|
|
|
|
!
|
|
|
|
|
! r4: Value to shift
|
2012-09-10 20:35:25 +00:00
|
|
|
! r5: Shift count
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Exit:
|
|
|
|
|
!
|
|
|
|
|
! r0: Result
|
|
|
|
|
!
|
|
|
|
|
! Destroys:
|
|
|
|
|
!
|
2012-09-10 20:35:25 +00:00
|
|
|
! T bit, r5
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
|
2000-08-16 21:17:40 +00:00
|
|
|
.global GLOBAL(ashrsi3)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(ashrsi3))
|
1995-04-27 18:08:43 -07:00
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|
|
.align 2
|
2000-08-16 21:17:40 +00:00
|
|
|
GLOBAL(ashrsi3):
|
1995-04-27 18:08:43 -07:00
|
|
|
mov #31,r0
|
1998-10-02 08:22:31 +00:00
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and r0,r5
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|
|
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mova LOCAL(ashrsi3_table),r0
|
1995-05-09 11:07:54 -07:00
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mov.b @(r0,r5),r5
|
1998-10-02 08:22:31 +00:00
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|
#ifdef __sh1__
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|
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add r5,r0
|
1995-04-27 18:08:43 -07:00
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jmp @r0
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1998-10-02 08:22:31 +00:00
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#else
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braf r5
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#endif
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1995-04-27 18:08:43 -07:00
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mov r4,r0
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1998-10-02 08:22:31 +00:00
|
|
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.align 2
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LOCAL(ashrsi3_table):
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.byte LOCAL(ashrsi3_0)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_1)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_2)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_3)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_4)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_5)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_6)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_7)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_8)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_9)-LOCAL(ashrsi3_table)
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|
|
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.byte LOCAL(ashrsi3_10)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_11)-LOCAL(ashrsi3_table)
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|
|
|
|
.byte LOCAL(ashrsi3_12)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_13)-LOCAL(ashrsi3_table)
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|
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|
.byte LOCAL(ashrsi3_14)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_15)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_16)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_17)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_18)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_19)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_20)-LOCAL(ashrsi3_table)
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|
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.byte LOCAL(ashrsi3_21)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_22)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_23)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_24)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_25)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_26)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_27)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_28)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_29)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_30)-LOCAL(ashrsi3_table)
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.byte LOCAL(ashrsi3_31)-LOCAL(ashrsi3_table)
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LOCAL(ashrsi3_31):
|
1995-04-27 18:08:43 -07:00
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rotcl r0
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rts
|
|
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subc r0,r0
|
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1998-10-02 08:22:31 +00:00
|
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LOCAL(ashrsi3_30):
|
1995-04-27 18:08:43 -07:00
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|
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shar r0
|
1998-10-02 08:22:31 +00:00
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LOCAL(ashrsi3_29):
|
1995-04-27 18:08:43 -07:00
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|
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shar r0
|
1998-10-02 08:22:31 +00:00
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LOCAL(ashrsi3_28):
|
1995-04-27 18:08:43 -07:00
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|
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shar r0
|
1998-10-02 08:22:31 +00:00
|
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LOCAL(ashrsi3_27):
|
1995-04-27 18:08:43 -07:00
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shar r0
|
1998-10-02 08:22:31 +00:00
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LOCAL(ashrsi3_26):
|
1995-04-27 18:08:43 -07:00
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|
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shar r0
|
1998-10-02 08:22:31 +00:00
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LOCAL(ashrsi3_25):
|
1995-04-27 18:08:43 -07:00
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shar r0
|
1998-10-02 08:22:31 +00:00
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LOCAL(ashrsi3_24):
|
1995-04-27 18:08:43 -07:00
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shlr16 r0
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shlr8 r0
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rts
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exts.b r0,r0
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|
|
|
|
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_23):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_22):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_21):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_20):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_19):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_18):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_17):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_16):
|
1995-04-27 18:08:43 -07:00
|
|
|
shlr16 r0
|
|
|
|
|
rts
|
|
|
|
|
exts.w r0,r0
|
|
|
|
|
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_15):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_14):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_13):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_12):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_11):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_10):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_9):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_8):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_7):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_6):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_5):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_4):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_3):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_2):
|
1995-04-27 18:08:43 -07:00
|
|
|
shar r0
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_1):
|
1995-04-27 18:08:43 -07:00
|
|
|
rts
|
|
|
|
|
shar r0
|
|
|
|
|
|
1998-10-02 08:22:31 +00:00
|
|
|
LOCAL(ashrsi3_0):
|
1995-04-27 18:08:43 -07:00
|
|
|
rts
|
|
|
|
|
nop
|
|
|
|
|
|
2002-12-16 18:23:00 +00:00
|
|
|
ENDFUNC(GLOBAL(ashrsi3))
|
1995-04-27 18:08:43 -07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef L_ashiftlt
|
|
|
|
|
|
|
|
|
|
!
|
2000-08-16 21:17:40 +00:00
|
|
|
! GLOBAL(ashlsi3)
|
2012-09-10 20:35:25 +00:00
|
|
|
! (For compatibility with older binaries, not used by compiler)
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Entry:
|
2012-09-10 20:35:25 +00:00
|
|
|
! r4: Value to shift
|
|
|
|
|
! r5: Shift count
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Exit:
|
2012-09-10 20:35:25 +00:00
|
|
|
! r0: Result
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Destroys:
|
2012-09-10 20:35:25 +00:00
|
|
|
! T bit
|
|
|
|
|
!
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
2012-09-10 20:35:25 +00:00
|
|
|
! GLOBAL(ashlsi3_r0)
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
2012-09-10 20:35:25 +00:00
|
|
|
! Entry:
|
|
|
|
|
! r4: Value to shift
|
|
|
|
|
! r0: Shift count
|
|
|
|
|
!
|
|
|
|
|
! Exit:
|
|
|
|
|
! r0: Result
|
|
|
|
|
!
|
|
|
|
|
! Destroys:
|
|
|
|
|
! T bit
|
|
|
|
|
|
2000-08-16 21:17:40 +00:00
|
|
|
.global GLOBAL(ashlsi3)
|
2012-09-10 20:35:25 +00:00
|
|
|
.global GLOBAL(ashlsi3_r0)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(ashlsi3))
|
2012-09-10 20:35:25 +00:00
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HIDDEN_FUNC(GLOBAL(ashlsi3_r0))
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2000-08-16 21:17:40 +00:00
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GLOBAL(ashlsi3):
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2012-09-10 20:35:25 +00:00
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mov r5,r0
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.align 2
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GLOBAL(ashlsi3_r0):
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1998-10-02 08:22:31 +00:00
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#ifdef __sh1__
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2012-09-10 20:35:25 +00:00
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and #31,r0
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shll2 r0
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mov.l r4,@-r15
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mov r0,r4
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mova LOCAL(ashlsi3_table),r0
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add r4,r0
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mov.l @r15+,r4
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1995-04-27 18:08:43 -07:00
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jmp @r0
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2012-09-10 20:35:25 +00:00
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mov r4,r0
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.align 2
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1998-10-02 08:22:31 +00:00
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#else
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2012-09-10 20:35:25 +00:00
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and #31,r0
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shll2 r0
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braf r0
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1995-04-27 18:08:43 -07:00
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mov r4,r0
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2012-09-10 20:35:25 +00:00
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#endif
|
1995-04-27 18:08:43 -07:00
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1998-10-02 08:22:31 +00:00
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LOCAL(ashlsi3_table):
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2012-09-10 20:35:25 +00:00
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rts // << 0
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nop
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LOCAL(ashlsi_1):
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rts // << 1
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shll r0
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LOCAL(ashlsi_2): // << 2
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1995-04-27 18:08:43 -07:00
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rts
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_1) // << 3
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1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_2) // << 4
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1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_5) // << 5
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1995-04-27 18:08:43 -07:00
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shll r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_6) // << 6
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1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_7) // << 7
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shll r0
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LOCAL(ashlsi_8): // << 8
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1995-04-27 18:08:43 -07:00
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rts
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shll8 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_8) // << 9
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shll r0
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bra LOCAL(ashlsi_8) // << 10
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1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_11) // << 11
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shll r0
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bra LOCAL(ashlsi_12) // << 12
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1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_13) // << 13
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shll r0
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bra LOCAL(ashlsi_14) // << 14
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1995-04-27 18:08:43 -07:00
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shll8 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_15) // << 15
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shll8 r0
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LOCAL(ashlsi_16): // << 16
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1995-04-27 18:08:43 -07:00
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rts
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2012-09-10 20:35:25 +00:00
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shll16 r0
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bra LOCAL(ashlsi_16) // << 17
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1995-04-27 18:08:43 -07:00
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shll r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_16) // << 18
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1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_19) // << 19
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shll r0
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bra LOCAL(ashlsi_20) // << 20
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1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_21) // << 21
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shll r0
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bra LOCAL(ashlsi_22) // << 22
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1995-04-27 18:08:43 -07:00
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shll16 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_23) // << 23
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shll16 r0
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bra LOCAL(ashlsi_16) // << 24
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shll8 r0
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bra LOCAL(ashlsi_25) // << 25
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shll r0
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bra LOCAL(ashlsi_26) // << 26
|
1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_27) // << 27
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shll r0
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bra LOCAL(ashlsi_28) // << 28
|
1995-04-27 18:08:43 -07:00
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shll2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(ashlsi_29) // << 29
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shll16 r0
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bra LOCAL(ashlsi_30) // << 30
|
1995-04-27 18:08:43 -07:00
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shll16 r0
|
2012-09-10 20:35:25 +00:00
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|
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and #1,r0 // << 31
|
1995-04-27 18:08:43 -07:00
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|
|
rts
|
2012-09-10 20:35:25 +00:00
|
|
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rotr r0
|
1995-04-27 18:08:43 -07:00
|
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|
2012-09-10 20:35:25 +00:00
|
|
|
LOCAL(ashlsi_7):
|
1995-04-27 18:08:43 -07:00
|
|
|
shll2 r0
|
2012-09-10 20:35:25 +00:00
|
|
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LOCAL(ashlsi_5):
|
|
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LOCAL(ashlsi_6):
|
1995-04-27 18:08:43 -07:00
|
|
|
shll2 r0
|
|
|
|
|
rts
|
2012-09-10 20:35:25 +00:00
|
|
|
LOCAL(ashlsi_13):
|
1995-04-27 18:08:43 -07:00
|
|
|
shll2 r0
|
2012-09-10 20:35:25 +00:00
|
|
|
LOCAL(ashlsi_12):
|
|
|
|
|
LOCAL(ashlsi_11):
|
|
|
|
|
shll8 r0
|
|
|
|
|
rts
|
|
|
|
|
LOCAL(ashlsi_21):
|
1995-04-27 18:08:43 -07:00
|
|
|
shll2 r0
|
2012-09-10 20:35:25 +00:00
|
|
|
LOCAL(ashlsi_20):
|
|
|
|
|
LOCAL(ashlsi_19):
|
|
|
|
|
shll16 r0
|
|
|
|
|
rts
|
|
|
|
|
LOCAL(ashlsi_28):
|
|
|
|
|
LOCAL(ashlsi_27):
|
1995-04-27 18:08:43 -07:00
|
|
|
shll2 r0
|
2012-09-10 20:35:25 +00:00
|
|
|
LOCAL(ashlsi_26):
|
|
|
|
|
LOCAL(ashlsi_25):
|
1995-04-27 18:08:43 -07:00
|
|
|
shll16 r0
|
2012-09-10 20:35:25 +00:00
|
|
|
rts
|
1995-04-27 18:08:43 -07:00
|
|
|
shll8 r0
|
2012-09-10 20:35:25 +00:00
|
|
|
|
|
|
|
|
LOCAL(ashlsi_22):
|
|
|
|
|
LOCAL(ashlsi_14):
|
|
|
|
|
shlr2 r0
|
1995-04-27 18:08:43 -07:00
|
|
|
rts
|
2012-09-10 20:35:25 +00:00
|
|
|
shll8 r0
|
1995-04-27 18:08:43 -07:00
|
|
|
|
2012-09-10 20:35:25 +00:00
|
|
|
LOCAL(ashlsi_23):
|
|
|
|
|
LOCAL(ashlsi_15):
|
|
|
|
|
shlr r0
|
1995-04-27 18:08:43 -07:00
|
|
|
rts
|
2012-09-10 20:35:25 +00:00
|
|
|
shll8 r0
|
|
|
|
|
|
|
|
|
|
LOCAL(ashlsi_29):
|
|
|
|
|
shlr r0
|
|
|
|
|
LOCAL(ashlsi_30):
|
|
|
|
|
shlr2 r0
|
|
|
|
|
rts
|
|
|
|
|
shll16 r0
|
1995-04-27 18:08:43 -07:00
|
|
|
|
2002-12-16 18:23:00 +00:00
|
|
|
ENDFUNC(GLOBAL(ashlsi3))
|
2012-09-10 20:35:25 +00:00
|
|
|
ENDFUNC(GLOBAL(ashlsi3_r0))
|
1995-04-27 18:08:43 -07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef L_lshiftrt
|
|
|
|
|
|
|
|
|
|
!
|
2000-08-16 21:17:40 +00:00
|
|
|
! GLOBAL(lshrsi3)
|
2012-09-10 20:35:25 +00:00
|
|
|
! (For compatibility with older binaries, not used by compiler)
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Entry:
|
2012-09-10 20:35:25 +00:00
|
|
|
! r4: Value to shift
|
|
|
|
|
! r5: Shift count
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Exit:
|
2012-09-10 20:35:25 +00:00
|
|
|
! r0: Result
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
|
|
|
|
! Destroys:
|
2012-09-10 20:35:25 +00:00
|
|
|
! T bit
|
|
|
|
|
!
|
|
|
|
|
!
|
|
|
|
|
! GLOBAL(lshrsi3_r0)
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
2012-09-10 20:35:25 +00:00
|
|
|
! Entry:
|
|
|
|
|
! r4: Value to shift
|
|
|
|
|
! r0: Shift count
|
|
|
|
|
!
|
|
|
|
|
! Exit:
|
|
|
|
|
! r0: Result
|
1995-04-27 18:08:43 -07:00
|
|
|
!
|
2012-09-10 20:35:25 +00:00
|
|
|
! Destroys:
|
|
|
|
|
! T bit
|
|
|
|
|
|
2000-08-16 21:17:40 +00:00
|
|
|
.global GLOBAL(lshrsi3)
|
2012-09-10 20:35:25 +00:00
|
|
|
.global GLOBAL(lshrsi3_r0)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(lshrsi3))
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2012-09-10 20:35:25 +00:00
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HIDDEN_FUNC(GLOBAL(lshrsi3_r0))
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2000-08-16 21:17:40 +00:00
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GLOBAL(lshrsi3):
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2012-09-10 20:35:25 +00:00
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mov r5,r0
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.align 2
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GLOBAL(lshrsi3_r0):
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1998-10-02 08:22:31 +00:00
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#ifdef __sh1__
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2012-09-10 20:35:25 +00:00
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and #31,r0
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shll2 r0
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mov.l r4,@-r15
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mov r0,r4
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mova LOCAL(lshrsi3_table),r0
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add r4,r0
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mov.l @r15+,r4
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1995-04-27 18:08:43 -07:00
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jmp @r0
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2012-09-10 20:35:25 +00:00
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mov r4,r0
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.align 2
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1998-10-02 08:22:31 +00:00
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#else
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2012-09-10 20:35:25 +00:00
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and #31,r0
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shll2 r0
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braf r0
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1995-04-27 18:08:43 -07:00
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mov r4,r0
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2012-09-10 20:35:25 +00:00
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#endif
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1998-10-02 08:22:31 +00:00
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LOCAL(lshrsi3_table):
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2012-09-10 20:35:25 +00:00
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rts // >> 0
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nop
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LOCAL(lshrsi_1): // >> 1
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rts
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shlr r0
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LOCAL(lshrsi_2): // >> 2
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1995-04-27 18:08:43 -07:00
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rts
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_1) // >> 3
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_2) // >> 4
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_5) // >> 5
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1995-04-27 18:08:43 -07:00
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shlr r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_6) // >> 6
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_7) // >> 7
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shlr r0
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LOCAL(lshrsi_8): // >> 8
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1995-04-27 18:08:43 -07:00
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rts
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shlr8 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_8) // >> 9
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shlr r0
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bra LOCAL(lshrsi_8) // >> 10
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_11) // >> 11
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shlr r0
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bra LOCAL(lshrsi_12) // >> 12
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_13) // >> 13
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shlr r0
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bra LOCAL(lshrsi_14) // >> 14
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shlr8 r0
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bra LOCAL(lshrsi_15) // >> 15
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1995-04-27 18:08:43 -07:00
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shlr8 r0
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2012-09-10 20:35:25 +00:00
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LOCAL(lshrsi_16): // >> 16
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1995-04-27 18:08:43 -07:00
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rts
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2012-09-10 20:35:25 +00:00
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shlr16 r0
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bra LOCAL(lshrsi_16) // >> 17
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1995-04-27 18:08:43 -07:00
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shlr r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_16) // >> 18
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_19) // >> 19
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shlr r0
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bra LOCAL(lshrsi_20) // >> 20
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_21) // >> 21
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shlr r0
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bra LOCAL(lshrsi_22) // >> 22
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1995-04-27 18:08:43 -07:00
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shlr16 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_23) // >> 23
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shlr16 r0
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bra LOCAL(lshrsi_16) // >> 24
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shlr8 r0
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bra LOCAL(lshrsi_25) // >> 25
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shlr r0
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bra LOCAL(lshrsi_26) // >> 26
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_27) // >> 27
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shlr r0
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bra LOCAL(lshrsi_28) // >> 28
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1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
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bra LOCAL(lshrsi_29) // >> 29
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shlr16 r0
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bra LOCAL(lshrsi_30) // >> 30
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1995-04-27 18:08:43 -07:00
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shlr16 r0
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2012-09-10 20:35:25 +00:00
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shll r0 // >> 31
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1995-04-27 18:08:43 -07:00
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rts
|
2012-09-10 20:35:25 +00:00
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movt r0
|
1995-04-27 18:08:43 -07:00
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|
2012-09-10 20:35:25 +00:00
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LOCAL(lshrsi_7):
|
1995-04-27 18:08:43 -07:00
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shlr2 r0
|
2012-09-10 20:35:25 +00:00
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LOCAL(lshrsi_5):
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LOCAL(lshrsi_6):
|
1995-04-27 18:08:43 -07:00
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shlr2 r0
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rts
|
2012-09-10 20:35:25 +00:00
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LOCAL(lshrsi_13):
|
1995-04-27 18:08:43 -07:00
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shlr2 r0
|
2012-09-10 20:35:25 +00:00
|
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LOCAL(lshrsi_12):
|
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LOCAL(lshrsi_11):
|
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shlr8 r0
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rts
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LOCAL(lshrsi_21):
|
1995-04-27 18:08:43 -07:00
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shlr2 r0
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2012-09-10 20:35:25 +00:00
|
|
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LOCAL(lshrsi_20):
|
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LOCAL(lshrsi_19):
|
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shlr16 r0
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|
rts
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LOCAL(lshrsi_28):
|
|
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LOCAL(lshrsi_27):
|
1995-04-27 18:08:43 -07:00
|
|
|
shlr2 r0
|
2012-09-10 20:35:25 +00:00
|
|
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LOCAL(lshrsi_26):
|
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LOCAL(lshrsi_25):
|
1995-04-27 18:08:43 -07:00
|
|
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shlr16 r0
|
2012-09-10 20:35:25 +00:00
|
|
|
rts
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1995-04-27 18:08:43 -07:00
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shlr8 r0
|
2012-09-10 20:35:25 +00:00
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|
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LOCAL(lshrsi_22):
|
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LOCAL(lshrsi_14):
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shll2 r0
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1995-04-27 18:08:43 -07:00
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rts
|
2012-09-10 20:35:25 +00:00
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shlr8 r0
|
1995-04-27 18:08:43 -07:00
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2012-09-10 20:35:25 +00:00
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|
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LOCAL(lshrsi_23):
|
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LOCAL(lshrsi_15):
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shll r0
|
1995-04-27 18:08:43 -07:00
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rts
|
2012-09-10 20:35:25 +00:00
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shlr8 r0
|
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LOCAL(lshrsi_29):
|
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shll r0
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LOCAL(lshrsi_30):
|
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shll2 r0
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rts
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shlr16 r0
|
1995-04-27 18:08:43 -07:00
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2002-12-16 18:23:00 +00:00
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ENDFUNC(GLOBAL(lshrsi3))
|
2012-09-10 20:35:25 +00:00
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ENDFUNC(GLOBAL(lshrsi3_r0))
|
1995-04-27 18:08:43 -07:00
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#endif
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2004-07-07 19:25:01 +00:00
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#ifdef L_movmem
|
1994-09-09 23:40:17 +00:00
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.text
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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.balign 4
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.global GLOBAL(movmem)
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HIDDEN_FUNC(GLOBAL(movmem))
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HIDDEN_ALIAS(movstr,movmem)
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/* This would be a lot simpler if r6 contained the byte count
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minus 64, and we wouldn't be called here for a byte count of 64. */
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GLOBAL(movmem):
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sts.l pr,@-r15
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shll2 r6
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bsr GLOBAL(movmemSI52+2)
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mov.l @(48,r5),r0
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.balign 4
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LOCAL(movmem_loop): /* Reached with rts */
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mov.l @(60,r5),r0
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add #-64,r6
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mov.l r0,@(60,r4)
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tst r6,r6
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mov.l @(56,r5),r0
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bt LOCAL(movmem_done)
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mov.l r0,@(56,r4)
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cmp/pl r6
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mov.l @(52,r5),r0
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add #64,r5
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mov.l r0,@(52,r4)
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add #64,r4
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bt GLOBAL(movmemSI52)
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1994-09-09 23:40:17 +00:00
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! done all the large groups, do the remainder
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2004-07-07 19:25:01 +00:00
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! jump to movmem+
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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mova GLOBAL(movmemSI4)+4,r0
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1994-09-09 23:40:17 +00:00
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add r6,r0
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jmp @r0
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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LOCAL(movmem_done): ! share slot insn, works out aligned.
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lds.l @r15+,pr
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mov.l r0,@(56,r4)
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mov.l @(52,r5),r0
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rts
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mov.l r0,@(52,r4)
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.balign 4
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2004-07-29 22:27:43 +00:00
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! ??? We need aliases movstr* for movmem* for the older libraries. These
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! aliases will be removed at the some point in the future.
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI64)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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|
|
HIDDEN_FUNC(GLOBAL(movmemSI64))
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HIDDEN_ALIAS(movstrSI64,movmemSI64)
|
2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI64):
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1994-09-09 23:40:17 +00:00
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mov.l @(60,r5),r0
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mov.l r0,@(60,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI60)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(movmemSI60))
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HIDDEN_ALIAS(movstrSI60,movmemSI60)
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI60):
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1994-09-09 23:40:17 +00:00
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mov.l @(56,r5),r0
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mov.l r0,@(56,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI56)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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|
|
HIDDEN_FUNC(GLOBAL(movmemSI56))
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|
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HIDDEN_ALIAS(movstrSI56,movmemSI56)
|
2004-07-07 19:25:01 +00:00
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|
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GLOBAL(movmemSI56):
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1994-09-09 23:40:17 +00:00
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mov.l @(52,r5),r0
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mov.l r0,@(52,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI52)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI52))
|
|
|
|
|
HIDDEN_ALIAS(movstrSI52,movmemSI52)
|
2004-07-07 19:25:01 +00:00
|
|
|
GLOBAL(movmemSI52):
|
1994-09-09 23:40:17 +00:00
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mov.l @(48,r5),r0
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mov.l r0,@(48,r4)
|
2004-07-07 19:25:01 +00:00
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|
.global GLOBAL(movmemSI48)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(movmemSI48))
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HIDDEN_ALIAS(movstrSI48,movmemSI48)
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI48):
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1994-09-09 23:40:17 +00:00
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mov.l @(44,r5),r0
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mov.l r0,@(44,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI44)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI44))
|
|
|
|
|
HIDDEN_ALIAS(movstrSI44,movmemSI44)
|
2004-07-07 19:25:01 +00:00
|
|
|
GLOBAL(movmemSI44):
|
1994-09-09 23:40:17 +00:00
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mov.l @(40,r5),r0
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mov.l r0,@(40,r4)
|
2004-07-07 19:25:01 +00:00
|
|
|
.global GLOBAL(movmemSI40)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI40))
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|
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HIDDEN_ALIAS(movstrSI40,movmemSI40)
|
2004-07-07 19:25:01 +00:00
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|
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GLOBAL(movmemSI40):
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1994-09-09 23:40:17 +00:00
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mov.l @(36,r5),r0
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mov.l r0,@(36,r4)
|
2004-07-07 19:25:01 +00:00
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|
.global GLOBAL(movmemSI36)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(movmemSI36))
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HIDDEN_ALIAS(movstrSI36,movmemSI36)
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI36):
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1994-09-09 23:40:17 +00:00
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mov.l @(32,r5),r0
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mov.l r0,@(32,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI32)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI32))
|
|
|
|
|
HIDDEN_ALIAS(movstrSI32,movmemSI32)
|
2004-07-07 19:25:01 +00:00
|
|
|
GLOBAL(movmemSI32):
|
1994-09-09 23:40:17 +00:00
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mov.l @(28,r5),r0
|
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mov.l r0,@(28,r4)
|
2004-07-07 19:25:01 +00:00
|
|
|
.global GLOBAL(movmemSI28)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI28))
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|
|
|
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HIDDEN_ALIAS(movstrSI28,movmemSI28)
|
2004-07-07 19:25:01 +00:00
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|
|
GLOBAL(movmemSI28):
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1994-09-09 23:40:17 +00:00
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mov.l @(24,r5),r0
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mov.l r0,@(24,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI24)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI24))
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|
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|
|
HIDDEN_ALIAS(movstrSI24,movmemSI24)
|
2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI24):
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1994-09-09 23:40:17 +00:00
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mov.l @(20,r5),r0
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mov.l r0,@(20,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI20)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(movmemSI20))
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HIDDEN_ALIAS(movstrSI20,movmemSI20)
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI20):
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1994-09-09 23:40:17 +00:00
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mov.l @(16,r5),r0
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mov.l r0,@(16,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI16)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(movmemSI16))
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HIDDEN_ALIAS(movstrSI16,movmemSI16)
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI16):
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1994-09-09 23:40:17 +00:00
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mov.l @(12,r5),r0
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mov.l r0,@(12,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI12)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI12))
|
|
|
|
|
HIDDEN_ALIAS(movstrSI12,movmemSI12)
|
2004-07-07 19:25:01 +00:00
|
|
|
GLOBAL(movmemSI12):
|
1994-09-09 23:40:17 +00:00
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mov.l @(8,r5),r0
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mov.l r0,@(8,r4)
|
2004-07-07 19:25:01 +00:00
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|
.global GLOBAL(movmemSI8)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(movmemSI8))
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HIDDEN_ALIAS(movstrSI8,movmemSI8)
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI8):
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1994-09-09 23:40:17 +00:00
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mov.l @(4,r5),r0
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mov.l r0,@(4,r4)
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmemSI4)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(movmemSI4))
|
|
|
|
|
HIDDEN_ALIAS(movstrSI4,movmemSI4)
|
2004-07-07 19:25:01 +00:00
|
|
|
GLOBAL(movmemSI4):
|
1994-09-09 23:40:17 +00:00
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mov.l @(0,r5),r0
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|
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rts
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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mov.l r0,@(0,r4)
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1994-09-09 23:40:17 +00:00
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2004-07-07 19:25:01 +00:00
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ENDFUNC(GLOBAL(movmemSI64))
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ENDFUNC(GLOBAL(movmemSI60))
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ENDFUNC(GLOBAL(movmemSI56))
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ENDFUNC(GLOBAL(movmemSI52))
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ENDFUNC(GLOBAL(movmemSI48))
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ENDFUNC(GLOBAL(movmemSI44))
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ENDFUNC(GLOBAL(movmemSI40))
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ENDFUNC(GLOBAL(movmemSI36))
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ENDFUNC(GLOBAL(movmemSI32))
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ENDFUNC(GLOBAL(movmemSI28))
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ENDFUNC(GLOBAL(movmemSI24))
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ENDFUNC(GLOBAL(movmemSI20))
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ENDFUNC(GLOBAL(movmemSI16))
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ENDFUNC(GLOBAL(movmemSI12))
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ENDFUNC(GLOBAL(movmemSI8))
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ENDFUNC(GLOBAL(movmemSI4))
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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ENDFUNC(GLOBAL(movmem))
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1994-09-09 23:40:17 +00:00
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#endif
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2004-07-07 19:25:01 +00:00
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#ifdef L_movmem_i4
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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.text
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2004-07-07 19:25:01 +00:00
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.global GLOBAL(movmem_i4_even)
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.global GLOBAL(movmem_i4_odd)
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.global GLOBAL(movmemSI12_i4)
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(movmem_i4_even))
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HIDDEN_FUNC(GLOBAL(movmem_i4_odd))
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HIDDEN_FUNC(GLOBAL(movmemSI12_i4))
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2002-12-16 18:23:00 +00:00
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_ALIAS(movstr_i4_even,movmem_i4_even)
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HIDDEN_ALIAS(movstr_i4_odd,movmem_i4_odd)
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HIDDEN_ALIAS(movstrSI12_i4,movmemSI12_i4)
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2004-07-29 22:27:43 +00:00
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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.p2align 5
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2004-07-07 19:25:01 +00:00
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L_movmem_2mod4_end:
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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mov.l r0,@(16,r4)
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rts
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mov.l r1,@(20,r4)
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.p2align 2
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmem_i4_even):
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2002-12-16 18:23:00 +00:00
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mov.l @r5+,r0
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2004-07-07 19:25:01 +00:00
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bra L_movmem_start_even
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2002-12-16 18:23:00 +00:00
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mov.l @r5+,r1
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmem_i4_odd):
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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mov.l @r5+,r1
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add #-4,r4
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mov.l @r5+,r2
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mov.l @r5+,r3
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mov.l r1,@(4,r4)
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mov.l r2,@(8,r4)
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2004-07-07 19:25:01 +00:00
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L_movmem_loop:
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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mov.l r3,@(12,r4)
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dt r6
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mov.l @r5+,r0
|
2004-07-07 19:25:01 +00:00
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bt/s L_movmem_2mod4_end
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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mov.l @r5+,r1
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add #16,r4
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2004-07-07 19:25:01 +00:00
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L_movmem_start_even:
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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mov.l @r5+,r2
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mov.l @r5+,r3
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mov.l r0,@r4
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dt r6
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mov.l r1,@(4,r4)
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2004-07-07 19:25:01 +00:00
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bf/s L_movmem_loop
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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mov.l r2,@(8,r4)
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rts
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mov.l r3,@(12,r4)
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2004-07-07 19:25:01 +00:00
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ENDFUNC(GLOBAL(movmem_i4_even))
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ENDFUNC(GLOBAL(movmem_i4_odd))
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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.p2align 4
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2004-07-07 19:25:01 +00:00
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GLOBAL(movmemSI12_i4):
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
mov.l @r5,r0
|
|
|
|
|
mov.l @(4,r5),r1
|
|
|
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mov.l @(8,r5),r2
|
|
|
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mov.l r0,@r4
|
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mov.l r1,@(4,r4)
|
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rts
|
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|
|
|
mov.l r2,@(8,r4)
|
2002-12-16 18:23:00 +00:00
|
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|
2004-07-07 19:25:01 +00:00
|
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|
ENDFUNC(GLOBAL(movmemSI12_i4))
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#endif
|
|
|
|
|
|
1994-09-09 23:40:17 +00:00
|
|
|
#ifdef L_mulsi3
|
|
|
|
|
|
|
|
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|
|
2000-08-16 21:17:40 +00:00
|
|
|
.global GLOBAL(mulsi3)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(mulsi3))
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1994-09-09 23:40:17 +00:00
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! r4 = aabb
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! r5 = ccdd
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! r0 = aabb*ccdd via partial products
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!
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! if aa == 0 and cc = 0
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! r0 = bb*dd
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!
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! else
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! aa = bb*dd + (aa*dd*65536) + (cc*bb*65536)
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!
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2000-08-16 21:17:40 +00:00
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GLOBAL(mulsi3):
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2001-03-11 02:16:40 +00:00
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mulu.w r4,r5 ! multiply the lsws macl=bb*dd
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1994-09-09 23:40:17 +00:00
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mov r5,r3 ! r3 = ccdd
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swap.w r4,r2 ! r2 = bbaa
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xtrct r2,r3 ! r3 = aacc
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tst r3,r3 ! msws zero ?
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1995-04-27 18:08:43 -07:00
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bf hiset
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1995-08-28 06:54:22 -04:00
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rts ! yes - then we have the answer
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1994-09-09 23:40:17 +00:00
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sts macl,r0
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hiset: sts macl,r0 ! r0 = bb*dd
|
2001-03-11 02:16:40 +00:00
|
|
|
mulu.w r2,r5 ! brewing macl = aa*dd
|
1994-09-09 23:40:17 +00:00
|
|
|
sts macl,r1
|
2001-03-11 02:16:40 +00:00
|
|
|
mulu.w r3,r4 ! brewing macl = cc*bb
|
1995-04-27 18:08:43 -07:00
|
|
|
sts macl,r2
|
1994-09-09 23:40:17 +00:00
|
|
|
add r1,r2
|
|
|
|
|
shll16 r2
|
|
|
|
|
rts
|
|
|
|
|
add r2,r0
|
1995-04-27 18:08:43 -07:00
|
|
|
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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ENDFUNC(GLOBAL(mulsi3))
|
1995-04-27 18:08:43 -07:00
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|
|
#endif
|
2013-06-09 21:32:37 +00:00
|
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|
|
/*------------------------------------------------------------------------------
|
|
|
|
|
32 bit signed integer division that uses FPU double precision division. */
|
|
|
|
|
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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#ifdef L_sdivsi3_i4
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1994-09-09 23:40:17 +00:00
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.title "SH DIVIDE"
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2013-06-09 21:32:37 +00:00
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2013-03-13 18:09:10 +00:00
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#if defined (__SH4__) || defined (__SH2A__)
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2013-06-09 21:32:37 +00:00
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/* This variant is used when FPSCR.PR = 1 (double precision) is the default
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setting.
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Args in r4 and r5, result in fpul, clobber dr0, dr2. */
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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2000-08-16 21:17:40 +00:00
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.global GLOBAL(sdivsi3_i4)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(sdivsi3_i4))
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2000-08-16 21:17:40 +00:00
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GLOBAL(sdivsi3_i4):
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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lds r4,fpul
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float fpul,dr0
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lds r5,fpul
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float fpul,dr2
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fdiv dr2,dr0
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rts
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ftrc dr0,fpul
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2002-12-16 18:23:00 +00:00
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ENDFUNC(GLOBAL(sdivsi3_i4))
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2013-06-09 21:32:37 +00:00
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2016-04-29 14:10:26 +00:00
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#elif defined (__SH2A_SINGLE__) || defined (__SH2A_SINGLE_ONLY__) || defined(__SH4_SINGLE__) || defined(__SH4_SINGLE_ONLY__)
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2013-06-09 21:32:37 +00:00
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/* This variant is used when FPSCR.PR = 0 (sigle precision) is the default
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setting.
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Args in r4 and r5, result in fpul, clobber r2, dr0, dr2.
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For this to work, we must temporarily switch the FPU do double precision,
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but we better do not touch FPSCR.FR. See PR 6526. */
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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2000-08-16 21:17:40 +00:00
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.global GLOBAL(sdivsi3_i4)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(sdivsi3_i4))
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2000-08-16 21:17:40 +00:00
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GLOBAL(sdivsi3_i4):
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2013-06-09 21:32:37 +00:00
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#ifndef __SH4A__
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mov.l r3,@-r15
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sts fpscr,r2
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mov #8,r3
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swap.w r3,r3 // r3 = 1 << 19 (FPSCR.PR bit)
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or r2,r3
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lds r3,fpscr // Set FPSCR.PR = 1.
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lds r4,fpul
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float fpul,dr0
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lds r5,fpul
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float fpul,dr2
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fdiv dr2,dr0
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ftrc dr0,fpul
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lds r2,fpscr
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
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|
rts
|
2013-06-09 21:32:37 +00:00
|
|
|
mov.l @r15+,r3
|
|
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|
#else
|
|
|
|
|
/* On SH4A we can use the fpchg instruction to flip the FPSCR.PR bit. */
|
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fpchg
|
|
|
|
|
lds r4,fpul
|
|
|
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|
float fpul,dr0
|
|
|
|
|
lds r5,fpul
|
|
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|
|
float fpul,dr2
|
|
|
|
|
fdiv dr2,dr0
|
|
|
|
|
ftrc dr0,fpul
|
|
|
|
|
rts
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|
|
|
fpchg
|
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#endif /* __SH4A__ */
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
|
2002-12-16 18:23:00 +00:00
|
|
|
ENDFUNC(GLOBAL(sdivsi3_i4))
|
2013-03-13 18:09:10 +00:00
|
|
|
#endif /* ! __SH4__ || __SH2A__ */
|
2013-06-09 21:32:37 +00:00
|
|
|
#endif /* L_sdivsi3_i4 */
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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2013-06-09 21:32:37 +00:00
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//------------------------------------------------------------------------------
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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#ifdef L_sdivsi3
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/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
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2003-01-24 15:45:53 +00:00
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sh2e/sh3e code. */
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1994-09-09 23:40:17 +00:00
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!!
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!! Steve Chamberlain
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!! sac@cygnus.com
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!!
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!!
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2002-12-16 18:23:00 +00:00
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!! args in r4 and r5, result in r0 clobber r1, r2, r3, and t bit
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1994-09-09 23:40:17 +00:00
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2000-08-16 21:17:40 +00:00
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.global GLOBAL(sdivsi3)
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Contribute sh64-elf.
2002-02-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (TARGET_CANNOT_MODIFY_JUMPS_P): Define to...
(sh_cannot_modify_jumps_p): New function.
2002-02-05 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (TARGET_MS_BITFIELD_LAYOUT_P): Define to...
(sh_ms_bitfield_layout_p): New function.
2002-02-04 Alexandre Oliva <aoliva@redhat.com>
Zack Weinberg <zack@codesourcery.com>
* config/sh/sh.h (TRAMPOLINE_ADJUST_ADDRESS): Use
expand_simple_binop instead of expand_binop.
2002-02-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (OVERRIDE_OPTIONS) [! TARGET_SH5]: Disable
use of .quad and .uaquad.
* config/sh/sh.c (TARGET_ASM_UNALIGNED_DI_OP,
TARGET_ASM_ALIGNED_DI_OP): Add comment pointing to the above.
2002-01-24 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (movdi_const, movdi_const_32bit,
movdi_const_16bit): Make sure all CONSTs have modes.
(sym2PIC): Ditto, but by adjusting all callers.
* config/sh/sh.c (calc_live_regs) [TARGET_SHCOMPACT]: Set pr_live
if the prologue calls the SHmedia argument decoder or register
saver.
2002-01-24 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (TARGET_ASM_UNALIGNED_DI_OP): Define.
(TARGET_ASM_ALIGNED_DI_OP): Likewise.
(sh_expand_epilogue): Don't emit USE of return target register.
(prepare_move_operands): Legitimize DImode PIC addresses.
(sh_media_register_for_return): Skip tr0, used to initialize the
PIC register.
(sh_expand_prologue): Remove explicit USE of return register.
(nonpic_symbol_mentioned_p): PC is non-PIC. Don't recurse in
CONST_DOUBLEs. UNSPEC_GOTPLT is PIC.
* config/sh/sh.h (ASM_OUTPUT_DOUBLE_INT): Removed, obsolete.
(OVERRIDE_OPTIONS): Don't disable PIC on SH5.
(EXTRA_CONSTRAINT_S): Use MOVI_SHORI_BASE_OPERAND_P instead of
EXTRA_CONSTRAINT_T.
(GOT_ENTRY_P, GOTPLT_ENTRY_P, GOTOFF_P, PIC_ADDR_P): New.
(MOVI_SHORI_BASE_OPERAND_P): New.
(NON_PIC_REFERENCE_P, PIC_REFERENCE_P): New.
(EXTRA_CONSTRAINT_T): Define in terms of them.
(OUTPUT_ADDR_CONST_EXTRA): Handle UNSPEC_GOTPLT.
* config/sh/sh.md (movsi_media, movsi_media_nofpu,
movdi_media, movdi_media_nofpu): Add SIBCALL_REGS class to
alternatives supporting TARGET_REGS.
(UNSPEC_GOTPLT): New constant.
(movdi split): Move incrementing of LABEL_NUSES...
(movdi_const, movdi_const_32bit): Here. Use
MOVI_SHORI_BASE_OPERAND_P instead of EXTRA_CONSTRAINT_T.
(movdi_const_16bit): New.
(call, call_value) [flag_pic]: Use GOTPLT.
(call_pop, call_value_pop): New expands.
(call_pop_compact, call_pop_rettramp): New insns.
(call_value_pop_compact, call_value_pop_rettramp): New insns.
(sibcall) [flag_pic]: Use GOT.
(builtint_setjmp_receiver): Remove bogus, unused expand.
(GOTaddr2picreg): Implement for SHcompact and SHmedia.
(*pt, *ptb, ptrel): New insns.
(sym2GOT): Handle DImode GOT.
(sym2GOTPLT, symGOTPLT2reg): New expands.
(sym2PIC): New expand.
(shcompact_return_tramp): Use GOTPLT to return trampoline.
(shcompact_return_tramp_i): Use return register explicitly.
* config/sh/sh.h (OVERRIDE_OPTIONS) [TARGET_SHMEDIA]: Don't
disable flag_reorder_blocks.
2002-01-19 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (sibcall_compact): Reorder return, uses and
clobbers, for clarity.
(sibcall_epilogue) [TARGET_SHCOMPACT]: Mark saving and
restoring of r0 in macl as MAYBE_DEAD.
2002-01-18 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (LONG_DOUBLE_TYPE_SIZE): Define.
* config/sh/sh.md (movv4sf_i, movv16sf_i): Fix uses of
alter_subreg all over.
(jump) [TARGET_SHMEDIA]: FAIL to create new jumps after
reload, instead of emitting instructions that would require
reloading.
(casesi_load_media): Add missing modes.
2001-11-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (sh_expand_prologue): Mark the PIC register
as used if the argument decoder is called.
2001-08-28 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (udivsi3, divsi3): Load libcall symbol name in
Pmode, then extend it to DImode if necessary.
2001-08-28 Stephen Clarke <Stephen.Clarke@st.com>
* config/sh/sh.h (LEGITIMATE_CONSTANT_P): Don't accept DFmode
constants in FPU-enabled SHmedia, let them be loaded from memory.
2001-08-28 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (cmpeqdi_media, cmpgtdi_media, cmpgtudi_media):
Adjust whitespace in assembly output templates.
2001-08-28 Stephen Clarke <Stephen.Clarke@st.com>
* config/sh/sh.md (movdicc_false, movdicc_true, movdicc): Adjust
mode of if_then_else.
2001-08-04 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh64.h (CPP_DEFAULT_CPU_SPEC): Override definition in
sh.h.
2001-07-26 Andrew Haley <aph@cambridge.redhat.com>
Joern Rennecke <amylaar@redhat.com>
* config/sh/sh64.h (CPP_DEFAULT_CPU_SPEC): New.
(SUBTARGET_CPP_PTR_SPEC): New.
(SUBTARGET_CPP_SPEC): Remove.
2001-07-06 Chandrakala Chavva <cchavva@redhat.com>
* config/sh/sh.md (movsf_media_nofpu+1, movdf_media_nofpu+1):
Fix typo in previous checkin.
2001-07-11 Chandrakala Chavva <cchavva@redhat.com>
* config/sh/sh.h (MODES_TIEABLE_P): Fix redact indentations.
2001-07-10 Chandrakala Chavva <cchavva@cygnus.com>
Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (MODES_TIEABLE_P): Don't tie modes wider than
what single FP register can hold for SHmedia target.
2001-07-06 Chandrakala Chavva <cchavva@redhat.com>
Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (movsf_media_nofpu+1, movdf_media_nofpu+1):
Do not split into SUBREG.
2001-06-14 Alexandre Oliva <aoliva@redhat.com>
* config/sh/ushmedia.h, config/sh/sshmedia.h: Updated signatures
and added new functions as specified in SH5 ABI r9.
2001-06-04 Alexandre Oliva <aoliva@redhat.com>
* config/sh/lib1funcs.asm (GCC_nested_trampoline): Align to an
8-byte boundary.
2001-06-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (dump_table): Add const0_rtx in calls of
gen_consttable_4 and gen_consttable_8. Emit multiple labels
and consttable_window_ends.
2001-06-03 Graham Stott <grahams@redhat,com>
* config/sh/sh.md (movdi split): Remove unused variable last_insn.
2001-05-16 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (print_operand): Handle floating-point pair,
vector and matrix registers.
* config/sh/sh.h (REGISTER_MOVE_COST): Take floating-pointer
vector modes into account.
* config/sh/sh.md (movv2sf): Split move between registers into
movdf.
(movv4sf, movv16sf): Introduce insns that get split only after
reload.
* config/sh/shmedia.h: Fix Copyright dates.
* config/sh/ushmedia.h: Likewise. Move loop counter
declarations into conditionals that uses them.
(sh_media_FVADD_S, sh_media_FVSUB_S): Fix off-by-one error in
loop boundary.
* config/sh/sshmedia.h: Fix Copyright dates.
(sh_media_PUTCFG): Fix constraints.
2001-05-12 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (TARGET_PTRMEMFUNC_VBIT_LOCATION): Define to
ptrmemfunc_vbit_in_delta for SH5.
2001-05-08 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (TARGET_SWITCHES): Document -m5-*.
* invoke.texi: Likewise.
2001-04-14 Alexandre Oliva <aoliva@redhat.com>
* config/sh/lib1funcs.asm (GCC_push_shmedia_regs,
GCC_push_shmedia_regs_nofpu, GCC_pop_shmedia_regs,
GCC_pop_shmedia_regs_nofpu): New global symbols.
* config/sh/t-sh64 (LIB1ASMFUNCS): Add them.
* config/sh/sh.h (SHMEDIA_REGS_STACK_ADJUST): New macro.
* config/sh/sh.c (calc_live_regs): Account for PR's saving in
compact function with nonlocal labels.
(sh_expand_prologue) [SHcompact]: Push SHmedia regs if needed.
(sh_expand_epilogue) [SHcompact]: Pop them when appropriate.
(initial_elimination_offset): Account for their stack space.
* config/sh/sh.md (shmedia_save_restore_regs_compact): New insn.
* config/sh/sh.md (movsi_media, movsi_media_nofpu, movqi_media,
movhi_media, movdi_media, movdi_media_nofpu, movdf_media,
movdf_media_nofpu, movsf_media, movsf_media_nofpu): Require at
least one of the operands to be a register.
(movv2sf): Likewise. Renamed to movv2sf_i.
(movdi, movdf, movv2sf, movv4sf, movv16sf, movsf):
prepare_move_operands() before emitting SHmedia insns.
2001-04-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/crti.asm (init, fini) [__SH5__ && ! __SHMEDIA__]:
Don't save nor initialize r12. Don't mis-align the stack.
Pad the code with a nop.
* config/sh/crti.asm: Don't restore r12. Don't mis-align the
stack.
2001-03-13 Alexandre Oliva <aoliva@redhat.com>
* gcc/longlong.h (__umulsidi3, count_leading_zeros)
[__SHMEDIA__]: Implement.
2001-03-11 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md: Set latency of `pt' closer to reality.
(movsi_media, movsi_media_nofpu, movdi_media, movdi_media_nofpu,
movdf_media, movdf_media_nofpu, movsf_media, movsf_media_nofpu):
Set move, load and store type attributes.
* config/sh/sh.c (sh_loop_align) [TARGET_SH5]: Set to 3.
* config/sh/sh.h (OVERRIDE_OPTIONS) [TARGET_SH5]: Disable
profiling.
* config/sh/sh.h (PROMOTE_MODE): Sign-extend SImode to DImode.
* config/sh/sh-protos.h (sh_media_register_for_return): Declare.
* config/sh/sh.c (sh_media_register_for_return): New function.
(sh_expand_prologue) [TARGET_SHMEDIA]: Copy r18 to an available
branch-target register.
(sh_expand_epilogue) [TARGET_SHMEDIA]: Explicitly USE it.
* config/sh/sh.md (return_media_i): Use any call-clobbered
branch-target register.
(return_media): If r18 wasn't copied in the prologue, copy it
here.
* config/sh/sh.h (CONDITIONAL_REGISTER_USAGE) [TARGET_SHMEDIA]:
Clear class FP0_REGS.
* config/sh/sh64.h (LINK_SPEC): Removed incorrect default copied
from elf.h.
2001-03-08 DJ Delorie <dj@redhat.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Disable relaxing for SHMEDIA.
2001-02-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (sibcall_compact): Set fp_mode to single.
2001-02-07 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (INT_ASM_OP) [SHMEDIA64]: Use `.quad'.
2001-02-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (INIT_CUMULATIVE_ARGS): Compute size of BLKmode
return value correctly for call_cookie.
2001-02-01 Alexandre Oliva <aoliva@redhat.com>
* config/sh/crt1.asm (start): Modified so as to call
___setup_argv_and_call_main.
2001-01-26 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Don't count stack_regs in
SHmedia mode.
2001-01-20 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (STRIP_DATALABEL_ENCODING): New macro.
(STRIP_NAME_ENCODING): Use it.
(ASM_OUTPUT_LABELREF): Likewise. Don't call assemble_name().
2001-01-19 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (sgeu) [! SHMEDIA]: Fix invocation of
prepare_scc_operands().
* config/sh/sh.h (SH_DATALABEL_ENCODING): Change to "#"...
(DATALABEL_SYMNAME_P): ... so that we don't need memcmp here.
2001-01-17 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (STRIP_NAME_ENCODING): Strip leading `*'.
2001-01-13 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (shcompact_incoming_args): Use R0_REG.
* config/sh/sh.md (R7_REG, R8_REG, R9_REG): Define as constants,
used in shcompact_incoming_args.
* config/sh/sh.c (sh_expand_epilogue): Fix thinko in previous
change.
* config/sh/crt1.asm (start) [SH5]: Switch to single-precision
mode.
* config/sh/lib1funcs.asm (sdivsi3_i4, udivsi3_i4, set_fpscr):
Adjust accordingly.
* config/sh/sh.c (sh_expand_prologue, sh_expand_epilogue):
Simplify. Adjust. Add sanity check.
* config/sh/sh.h (TARGET_SWITCHES) [5-compact]: Set
FPU_SINGLE_BIT.
* config/sh/sh.md (udivsi3_i4_single, divsi3_i4_single): Match
TARGET_SHCOMPACT.
(udivsi3, divsi3): Use them.
(force_mode_for_call): New insn.
(call, call_value, sibcall_value): Emit it before SHcompact
calls.
2001-01-11 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (call, call_value, sibcall): Make sure the
call cookie is non-NULL before taking its value.
2001-01-10 Alexandre Oliva <aoliva@redhat.com>
* config.gcc (sh64): Set target_requires_64bit_host_wide_int.
2001-01-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (shcompact_incoming_args): Set argument memory
block.
* config/sh/sh.h (STATIC_CHAIN_REGNUM) [SH5]: Use r1.
* config/sh/sh.c (sh_expand_prologue) [SH5]: Use r0 as
temporary for stack adjusts. Use MACL and MACH to pass
arguments to shcompact_incoming_args.
* config/sh/sh.md (shcompact_incoming_args): Adjust. Don't
clobber r1.
* config/sh/lib1funcs.asm (shcompact_incoming_args): Likewise.
(nested_trampoline): Load static chain address into r1.
* config/sh/sh.md (movdi_media splits): Fix sign-extension.
2001-01-07 Alexandre Oliva <aoliva@redhat.com
* config/sh/sh.c (fpul_operand) [SHMEDIA]: Just call
fp_arith_reg_operand().
2001-01-06 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (casesi): Sign-extend the first two operands,
and use signed compares for them.
* config/sh/sh.c (dump_table): Don't emit 8-byte constants after
4-byte ones. Instead, inter-leave them, maintaining the 8-byte
ones properly aligned.
(find_barrier): Account for extra alignment needed for 8-byte wide
constants.
(machine_dependent_reorg): Require a label for the second 4-byte
constant after an 8-byte one.
* config/sh/lib1funcs.asm (sdivsi3): Fix typo in yesterday's
change.
2001-01-05 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (machine_dependent_reorg) [SHCOMPACT]: Reset
last_float when switching float modes.
* config/sh/sh.md (movdf) [SH5]: Don't use stack-pointer
auto-increment for general-purpose registers.
* config/sh/lib1funcs.asm (sdivsi3) [SHMEDIA]: Sign-extend the
result.
* config/sh/sh.c (sh_expand_prologue) [SH5]: Use r1 as temporary
for stack adjust.
* config/sh/sh.c (sh_builtin_saveregs): Support using all
registers for varargs.
2001-01-01 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Simplify.
* config/sh/sh.h (CALL_COOKIE_STACKSEQ,
CALL_COOKIE_STACKSEQ_SHIFT, CALL_COOKIE_STACKSEQ_GET): New macros.
(CALL_COOKIE_INT_REG_SHIFT): Adjust.
(FUNCTION_ARG_ADVANCE): Use SHCOMPACT_FORCE_ON_STACK. Adjust
call_cookie accordingly.
(FUNCTION_ARG): Test SHCOMPACT_FORCE_ON_STACK.
(SHCOMPACT_BYREF): Likewise.
(SHCOMPACT_FORCE_ON_STACK): New macro.
* config/sh/sh.c (sh_expand_prologue): Use new call_cookie format.
(sh_builtin_saveregs): Likewise.
* config/sh/lib1funcs.asm (shcompact_call_trampoline,
shcompact_incoming_args): Use new shift values. Support
sequences of consecutive and non-consecutive pushes/pops.
* config/sh/sh.md (return): Don't explicitly use PR_REG.
2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com>
* config/sh/sh.h (TEXT_SECTION): Define.
* config/sh/elf.h (ASM_FILE_START): Output TEXT_SECTION_ASM_OP.
2001-01-05 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (INIT_CUMULATIVE_LIBCALL_ARGS): New macro.
* config/sh/sh.h (BASE_RETURN_VALUE_REG): Use FP regs for
return values on FPU-enabled SHmedia.
(FUNCTION_VALUE_REGNO_P): Mark FIRST_FP_RET_REG as used on
FPU-enabled SHmedia.
(INIT_CUMULATIVE_ARGS): Set up return trampoline only if
value is returned in a non-FP reg and is not returned by
reference.
* config/sh/sh.md (shcompact_return_tramp_i): Change type to
jump_ind.
2000-01-04 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (SH_MIN_ALIGN_FOR_CALLEE_COPY): New.
(FUNCTION_ARG_CALLEE_COPIES): Require argument to be
quad-aligned to be passed by callee-copy reference.
2001-01-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/elf.h (MAX_WCHAR_TYPE_SIZE): Define.
* config/sh/sh64.h (MAX_WCHAR_TYPE_SIZE): Undefine.
2001-01-02 Alexandre Oliva <aoliva@redhat.com>
* config/sh/lib1funcs.asm (shcompact_call_trampoline): Fix error in
copying low-numbered FP regs to r7 and r8.
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Don't request copying of
FP regs to general-purpose regs only if the copy was passed on the
stack.
* config/sh/lib1funcs.asm (shcompact_call_trampoline): Fix typo in
copying FP reg to r9.
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Use trampoline to
copy FP regs to general-purpose regs only in outgoing calls.
* config/sh/sh.md (movdf_media, movsf_media): Revert incorrect
change from 2000-10-30. Adjust for 64-bit (or 32-bit)
HOST_WIDE_INT.
* config/sh/sh.h (struct sh_args): Document all fields.
(FUNCTION_OK_FOR_SIBCALL): Functions that receive arguments
passed partially on the stack should not consider making
sibcalls.
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Add byref regs to
stack_regs only for incoming calls. When passing FP args,
make sure there are FP regs available before modifying
call_cookie.
(SHCOMPACT_BYREF): Pass double args in general-purpose
registers by reference.
2000-12-30 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (FUNCTION_OK_FOR_SIBCALL) [SHCOMPACT]: Don't
attempt to generate sibcalls if the caller got any arguments
by reference.
* config/sh/lib1funcs.asm (set_fpscr) [SH5]: Default to double.
* config/sh/sh.c (dump_table) [SHCOMPACT]: Align DImode and DFmode
to 8-byte boundaries.
* config/sh/sh.md (shcompact_preserve_incoming_args): New insn.
* config/sh/sh.h (CALL_COOKIE_INT_REG_GET): New macro.
* config/sh/sh.c (sh_expand_prologue): Preserve args that will be
stored in the stack.
* config/sh/lib1funcs.asm (ct_main_table, ia_main_table): Arrange
for the offsets to have the ISA bit set.
(shcompact_call_trampoline): Document. Swap r0 and r1, to match
invocation. Use beq instead of bgt to mark end of sequence of
loads.
(shcompact_incoming_args): Fix store of r2. Use beq instead of
bgt to mark end of sequence of stores.
* config/sh/sh.c (arith_operand): Don't check whether
CONST_OK_FOR_J for now.
* config/sh/sh.md (movdf_media, movsf_media): Use HOST_WIDE_INT
instead of long for conversion.
2000-12-29 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (print_operand_address): Convert INTVAL to int
before passing it to fprintf.
2000-12-28 Alexandre Oliva <aoliva@redhat.com>
* config/sh/crt1.asm (start): Reset SR.FD, to enable the FP unit.
Call set_fpscr before reading/writing SR.
* config/sh/crt1.asm (start): Set SR.SZ and SR.PR, but not SR.FR.
Call set_fpscr.
* config/sh/lib1funcs.asm: Add `.align 2' directives before
SHmedia code.
(FMOVD_WORKS): Define on SH5 with FPU.
(set_fpscr): Define on SH5. Remove separate _fpscr_values
setting.
* config/sh/t-sh64 (LIB1ASMFUNCS): Add _set_fpscr instead of
_fpscr_values.
2000-12-28 Hans-Peter Nilsson <hpn@cygnus.com>
* config/sh/lib1funcs.asm (ct_main_table): Align contents to even
address.
(ia_main_table): Ditto.
2000-12-27 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (MAX_WCHAR_TYPE_SIZE): Don't define.
* config/sh/sh64.h (WCHAR_TYPE, WCHAR_TYPE_SIZE): Reinstate
the definitions from sh.h.
* config/sh/sh.h (PTRDIFF_TYPE): Define as conditional on
TARGET_SH5.
(SUBTARGET_CPP_SPEC): Arrange for __PTRDIFF_TYPE__ to be defined.
* config/sh/elf.h (PTRDIFF_TYPE): Likewise.
* config/sh/sh64.h (SUBTARGET_CPP_SPEC): Likewise.
2000-12-26 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (movdi_media split): Don't add REG_LABEL notes.
Increment LABEL_NUSES.
From-SVN: r49630
2002-02-09 03:08:08 +00:00
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2016-04-29 14:10:26 +00:00
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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FUNC(GLOBAL(sdivsi3))
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2000-08-16 21:17:40 +00:00
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GLOBAL(sdivsi3):
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1994-09-09 23:40:17 +00:00
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mov r4,r1
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mov r5,r0
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1995-04-27 18:08:43 -07:00
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1994-09-09 23:40:17 +00:00
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tst r0,r0
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bt div0
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mov #0,r2
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div0s r2,r1
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subc r3,r3
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subc r2,r1
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div0s r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
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rotcl r1
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div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
div1 r0,r3
|
|
|
|
|
rotcl r1
|
|
|
|
|
addc r2,r1
|
1995-04-27 18:08:43 -07:00
|
|
|
rts
|
1994-09-09 23:40:17 +00:00
|
|
|
mov r1,r0
|
|
|
|
|
|
1995-04-27 18:08:43 -07:00
|
|
|
|
1994-09-09 23:40:17 +00:00
|
|
|
div0: rts
|
|
|
|
|
mov #0,r0
|
|
|
|
|
|
2002-12-16 18:23:00 +00:00
|
|
|
ENDFUNC(GLOBAL(sdivsi3))
|
2013-06-09 21:32:37 +00:00
|
|
|
#endif /* L_sdivsi3 */
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------
|
|
|
|
|
32 bit unsigned integer division that uses FPU double precision division. */
|
1994-09-09 23:40:17 +00:00
|
|
|
|
2013-06-09 21:32:37 +00:00
|
|
|
#ifdef L_udivsi3_i4
|
1994-09-09 23:40:17 +00:00
|
|
|
.title "SH DIVIDE"
|
2013-06-09 21:32:37 +00:00
|
|
|
|
2013-03-13 18:09:10 +00:00
|
|
|
#if defined (__SH4__) || defined (__SH2A__)
|
2013-06-09 21:32:37 +00:00
|
|
|
/* This variant is used when FPSCR.PR = 1 (double precision) is the default
|
|
|
|
|
setting.
|
|
|
|
|
Args in r4 and r5, result in fpul,
|
|
|
|
|
clobber r0, r1, r4, r5, dr0, dr2, dr4, and t bit */
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
|
2000-08-16 21:17:40 +00:00
|
|
|
.global GLOBAL(udivsi3_i4)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(udivsi3_i4))
|
2000-08-16 21:17:40 +00:00
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|
|
GLOBAL(udivsi3_i4):
|
2013-06-09 21:32:37 +00:00
|
|
|
mov #1,r1
|
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|
|
|
cmp/hi r1,r5
|
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|
bf/s trivial
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|
rotr r1
|
|
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xor r1,r4
|
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lds r4,fpul
|
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|
|
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mova L1,r0
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#ifdef FMOVD_WORKS
|
2013-06-09 21:32:37 +00:00
|
|
|
fmov.d @r0+,dr4
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#else
|
2013-06-09 21:32:37 +00:00
|
|
|
fmov.s @r0+,DR40
|
|
|
|
|
fmov.s @r0,DR41
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#endif
|
2013-06-09 21:32:37 +00:00
|
|
|
float fpul,dr0
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xor r1,r5
|
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lds r5,fpul
|
|
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|
|
float fpul,dr2
|
|
|
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fadd dr4,dr0
|
|
|
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fadd dr4,dr2
|
|
|
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fdiv dr2,dr0
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
rts
|
2013-06-09 21:32:37 +00:00
|
|
|
ftrc dr0,fpul
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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trivial:
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rts
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2013-06-09 21:32:37 +00:00
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lds r4,fpul
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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.align 2
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2000-04-06 18:19:44 +00:00
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#ifdef FMOVD_WORKS
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2013-06-09 21:32:37 +00:00
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.align 3 // Make the double below 8 byte aligned.
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2000-04-06 18:19:44 +00:00
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#endif
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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L1:
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.double 2147483648
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2002-12-16 18:23:00 +00:00
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ENDFUNC(GLOBAL(udivsi3_i4))
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2013-06-09 21:32:37 +00:00
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2013-03-13 18:09:10 +00:00
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#elif defined (__SH2A_SINGLE__) || defined (__SH2A_SINGLE_ONLY__) || defined(__SH4_SINGLE__) || defined(__SH4_SINGLE_ONLY__)
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2013-06-09 21:32:37 +00:00
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/* This variant is used when FPSCR.PR = 0 (sigle precision) is the default
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setting.
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Args in r4 and r5, result in fpul,
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clobber r0, r1, r4, r5, dr0, dr2, dr4.
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For this to work, we must temporarily switch the FPU do double precision,
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but we better do not touch FPSCR.FR. See PR 6526. */
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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2000-08-16 21:17:40 +00:00
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.global GLOBAL(udivsi3_i4)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(udivsi3_i4))
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2000-08-16 21:17:40 +00:00
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GLOBAL(udivsi3_i4):
|
2013-06-09 21:32:37 +00:00
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#ifndef __SH4A__
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mov #1,r1
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cmp/hi r1,r5
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bf/s trivial
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rotr r1 // r1 = 1 << 31
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sts.l fpscr,@-r15
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xor r1,r4
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mov.l @(0,r15),r0
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xor r1,r5
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mov.l L2,r1
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lds r4,fpul
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or r0,r1
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mova L1,r0
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lds r1,fpscr
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#ifdef FMOVD_WORKS
|
2013-06-09 21:32:37 +00:00
|
|
|
fmov.d @r0+,dr4
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#else
|
2013-06-09 21:32:37 +00:00
|
|
|
fmov.s @r0+,DR40
|
|
|
|
|
fmov.s @r0,DR41
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#endif
|
2013-06-09 21:32:37 +00:00
|
|
|
float fpul,dr0
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|
|
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lds r5,fpul
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|
float fpul,dr2
|
|
|
|
|
fadd dr4,dr0
|
|
|
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fadd dr4,dr2
|
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|
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fdiv dr2,dr0
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|
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ftrc dr0,fpul
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
rts
|
2013-06-09 21:32:37 +00:00
|
|
|
lds.l @r15+,fpscr
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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2000-04-06 18:19:44 +00:00
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#ifdef FMOVD_WORKS
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2013-06-09 21:32:37 +00:00
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.align 3 // Make the double below 8 byte aligned.
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2000-04-06 18:19:44 +00:00
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#endif
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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trivial:
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rts
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2013-06-09 21:32:37 +00:00
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lds r4,fpul
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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.align 2
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2013-06-09 21:32:37 +00:00
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L2:
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#ifdef FMOVD_WORKS
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.long 0x180000 // FPSCR.PR = 1, FPSCR.SZ = 1
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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#else
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2013-06-09 21:32:37 +00:00
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.long 0x80000 // FPSCR.PR = 1
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#endif
|
2013-06-09 21:32:37 +00:00
|
|
|
L1:
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
.double 2147483648
|
|
|
|
|
|
2013-06-09 21:32:37 +00:00
|
|
|
#else
|
|
|
|
|
/* On SH4A we can use the fpchg instruction to flip the FPSCR.PR bit.
|
|
|
|
|
Although on SH4A fmovd usually works, it would require either additional
|
|
|
|
|
two fschg instructions or an FPSCR push + pop. It's not worth the effort
|
|
|
|
|
for loading only one double constant. */
|
|
|
|
|
mov #1,r1
|
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cmp/hi r1,r5
|
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|
|
bf/s trivial
|
|
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|
|
rotr r1 // r1 = 1 << 31
|
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|
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fpchg
|
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|
|
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mova L1,r0
|
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|
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xor r1,r4
|
|
|
|
|
fmov.s @r0+,DR40
|
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|
|
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lds r4,fpul
|
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|
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fmov.s @r0,DR41
|
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|
|
xor r1,r5
|
|
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|
|
float fpul,dr0
|
|
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|
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lds r5,fpul
|
|
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|
|
float fpul,dr2
|
|
|
|
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fadd dr4,dr0
|
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|
|
|
fadd dr4,dr2
|
|
|
|
|
fdiv dr2,dr0
|
|
|
|
|
ftrc dr0,fpul
|
|
|
|
|
rts
|
|
|
|
|
fpchg
|
|
|
|
|
|
|
|
|
|
trivial:
|
|
|
|
|
rts
|
|
|
|
|
lds r4,fpul
|
|
|
|
|
|
|
|
|
|
.align 2
|
|
|
|
|
L1:
|
|
|
|
|
.double 2147483648
|
|
|
|
|
|
|
|
|
|
#endif /* __SH4A__ */
|
|
|
|
|
|
|
|
|
|
|
2002-12-16 18:23:00 +00:00
|
|
|
ENDFUNC(GLOBAL(udivsi3_i4))
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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#endif /* ! __SH4__ */
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2013-06-09 21:32:37 +00:00
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#endif /* L_udivsi3_i4 */
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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#ifdef L_udivsi3
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/* __SH4_SINGLE_ONLY__ keeps this part for link compatibility with
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2003-01-24 15:45:53 +00:00
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sh2e/sh3e code. */
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1994-09-09 23:40:17 +00:00
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1995-03-22 14:56:26 -08:00
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!! args in r4 and r5, result in r0, clobbers r4, pr, and t bit
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2000-08-16 21:17:40 +00:00
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.global GLOBAL(udivsi3)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(udivsi3))
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1994-09-09 23:40:17 +00:00
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lib1funcs.asm (sdivsi3): Add optimized SH64 implementations.
* lib1funcs.asm (sdivsi3): Add optimized SH64 implementations.
(udivsi3): Likewise. Rewrite SH1 implementation.
(udivdi3, divdi3, umoddi3, moddi3): New SHmedia functions.
* sh.md (R20_REG, R21_REG, R22_REG, R23_REG, FR23_REG): New constants.
(udivsi3_i1_media, divsi3_i1_media): Fix clobber list.
* config/sh/t-sh64 (LIB1ASMFUNCS): (_udivdi3, _divdi3, _umoddi3): Add.
(_moddi3): Likewise.
* lib1funcs.asm (ic_invalidate): Add data cache line writeback.
From-SVN: r54965
2002-06-24 20:08:17 +00:00
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LOCAL(div8):
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div1 r5,r4
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LOCAL(div7):
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div1 r5,r4; div1 r5,r4; div1 r5,r4
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div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
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LOCAL(divx4):
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div1 r5,r4; rotcl r0
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div1 r5,r4; rotcl r0
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div1 r5,r4; rotcl r0
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rts; div1 r5,r4
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GLOBAL(udivsi3):
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sts.l pr,@-r15
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extu.w r5,r0
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cmp/eq r5,r0
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#ifdef __sh1__
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bf LOCAL(large_divisor)
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#else
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bf/s LOCAL(large_divisor)
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#endif
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div0u
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swap.w r4,r0
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shlr16 r4
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bsr LOCAL(div8)
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shll16 r5
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bsr LOCAL(div7)
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div1 r5,r4
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xtrct r4,r0
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xtrct r0,r4
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bsr LOCAL(div8)
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swap.w r4,r4
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bsr LOCAL(div7)
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div1 r5,r4
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lds.l @r15+,pr
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xtrct r4,r0
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swap.w r0,r0
|
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rotcl r0
|
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rts
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shlr16 r5
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LOCAL(large_divisor):
|
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#ifdef __sh1__
|
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div0u
|
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#endif
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mov #0,r0
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xtrct r4,r0
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xtrct r0,r4
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|
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bsr LOCAL(divx4)
|
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|
rotcl r0
|
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bsr LOCAL(divx4)
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rotcl r0
|
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bsr LOCAL(divx4)
|
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|
rotcl r0
|
|
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bsr LOCAL(divx4)
|
|
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|
rotcl r0
|
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|
lds.l @r15+,pr
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rts
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rotcl r0
|
1994-09-09 23:40:17 +00:00
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2002-12-16 18:23:00 +00:00
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ENDFUNC(GLOBAL(udivsi3))
|
lib1funcs.asm (sdivsi3): Add optimized SH64 implementations.
* lib1funcs.asm (sdivsi3): Add optimized SH64 implementations.
(udivsi3): Likewise. Rewrite SH1 implementation.
(udivdi3, divdi3, umoddi3, moddi3): New SHmedia functions.
* sh.md (R20_REG, R21_REG, R22_REG, R23_REG, FR23_REG): New constants.
(udivsi3_i1_media, divsi3_i1_media): Fix clobber list.
* config/sh/t-sh64 (LIB1ASMFUNCS): (_udivdi3, _divdi3, _umoddi3): Add.
(_moddi3): Likewise.
* lib1funcs.asm (ic_invalidate): Add data cache line writeback.
From-SVN: r54965
2002-06-24 20:08:17 +00:00
|
|
|
#endif /* L_udivsi3 */
|
|
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|
1998-10-02 08:22:31 +00:00
|
|
|
#ifdef L_set_fpscr
|
Introduce sh2a support.
2004-07-29 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Build multilibs for sh2a and sh2a-single by
default.
* config/sh/sh.h (SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Define by
default. Split their tests out of the corresponding SH4
multilibs.
* config/sh/t-sh (MULTILIB_MATCHES): Don't ever use SH4 or SH4a
multilibs for SH2a.
2004-07-28 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Handle sh2a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh2a command line flags.
* config/sh/t-mlib-sh2a: New.
* config/sh/t-mlib-sh2a-nofpu: New.
* config/sh/t-mlib-sh2a-single: New.
* config/sh/t-mlib-sh2a-single-only: New.
2004-07-09 Nick Clifton <nickc@redhat.com>
Issue 43400
* config/sh/sh.h (DRIVER_SELF_SPECS): Issue an error message if
-ml and -m2a are used together.
2004-03-23 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (sh_builtin_saveregs): Use the double code only
when we have a double-sized FPU.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/lib1funcs.asm (set_fpscr): Don't build if __SH2A_NOFPU__
is set.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Add cases for -msh2a-nofpu,
-msh2a-single and -msh2a-single-only
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/crt1.asm: Don't generate FPU instructions if __SH2A_NOFPU__
is set.
2004-02-20 DJ Delorie <dj@delorie.com>
* config/sh/sh.md (movsf_i, movsf_ie, movsf, ble, bge): Disable for sh2a-nofpu.
2004-02-20 Fred Fish <fnf@redhat.com>,
Corinna Vinschen <vinschen@redhat.com>
* config/sh/t-sh (MULTILIB_OPTIONS): Add 2a-nofpu.
(MULTILIB_EXCEPTIONS): Don't build littel-endian on sh2a.
2004-02-18 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (broken_move): Add support for movi20.
* config/sh/sh.h: Likewise.
(SHIFT_COUNT_TRUNCATED): Set for sh2a.
* config/sh/sh.md (udivsi3_sh2a): New.
(udivsi3): Call it.
(divsi3_sh2a): New.
(divsi3): Call it.
(mul_r): New.
(ashlsi3_sh2a): New.
(ashrsi3_sh2a): New.
(lshrsi3_sh2a): New.
(movsi_i): Disable for sh2a.
(movsi_ie): Add movi20.
(movsf_i, movsf_ie, movsf, ble, untyped_call): Explicitly enable
sh2a, for -m2a-nofpu mode.
2004-02-13 DJ Delorie <dj@redhat.com>
* config/sh/lib1funcs.asm: Handle double vs single better.
* config/sh/sh.h: Likewise.
2004-02-09 DJ Delorie <dj@redhat.com>
* config/sh/crt1.asm: Add support for sh2a.
* config/sh/elf.h: Likewise.
* config/sh/lib1funcs.asm: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/t-sh: Likewise.
From-SVN: r85286
2004-07-29 06:10:03 +00:00
|
|
|
#if !defined (__SH2A_NOFPU__)
|
2016-04-29 14:10:26 +00:00
|
|
|
#if defined (__SH2E__) || defined (__SH2A__) || defined (__SH3E__) || defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
|
2000-08-16 21:17:40 +00:00
|
|
|
.global GLOBAL(set_fpscr)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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HIDDEN_FUNC(GLOBAL(set_fpscr))
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2000-08-16 21:17:40 +00:00
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GLOBAL(set_fpscr):
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1998-10-02 08:22:31 +00:00
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lds r4,fpscr
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2003-08-12 01:25:07 +00:00
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#ifdef __PIC__
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mov.l r12,@-r15
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2007-04-25 08:03:55 +00:00
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#ifdef __vxworks
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mov.l LOCAL(set_fpscr_L0_base),r12
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mov.l LOCAL(set_fpscr_L0_index),r0
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mov.l @r12,r12
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mov.l @(r0,r12),r12
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#else
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2003-08-12 01:25:07 +00:00
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mova LOCAL(set_fpscr_L0),r0
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mov.l LOCAL(set_fpscr_L0),r12
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add r0,r12
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2007-04-25 08:03:55 +00:00
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#endif
|
2003-08-12 01:25:07 +00:00
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|
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mov.l LOCAL(set_fpscr_L1),r0
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mov.l @(r0,r12),r1
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mov.l @r15+,r12
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#else
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2000-08-16 21:17:40 +00:00
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mov.l LOCAL(set_fpscr_L1),r1
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2003-08-12 01:25:07 +00:00
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#endif
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1998-10-02 08:22:31 +00:00
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swap.w r4,r0
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or #24,r0
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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#ifndef FMOVD_WORKS
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1998-10-02 08:22:31 +00:00
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xor #16,r0
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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#endif
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Introduce sh2a support.
2004-07-29 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Build multilibs for sh2a and sh2a-single by
default.
* config/sh/sh.h (SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Define by
default. Split their tests out of the corresponding SH4
multilibs.
* config/sh/t-sh (MULTILIB_MATCHES): Don't ever use SH4 or SH4a
multilibs for SH2a.
2004-07-28 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Handle sh2a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh2a command line flags.
* config/sh/t-mlib-sh2a: New.
* config/sh/t-mlib-sh2a-nofpu: New.
* config/sh/t-mlib-sh2a-single: New.
* config/sh/t-mlib-sh2a-single-only: New.
2004-07-09 Nick Clifton <nickc@redhat.com>
Issue 43400
* config/sh/sh.h (DRIVER_SELF_SPECS): Issue an error message if
-ml and -m2a are used together.
2004-03-23 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (sh_builtin_saveregs): Use the double code only
when we have a double-sized FPU.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/lib1funcs.asm (set_fpscr): Don't build if __SH2A_NOFPU__
is set.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Add cases for -msh2a-nofpu,
-msh2a-single and -msh2a-single-only
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/crt1.asm: Don't generate FPU instructions if __SH2A_NOFPU__
is set.
2004-02-20 DJ Delorie <dj@delorie.com>
* config/sh/sh.md (movsf_i, movsf_ie, movsf, ble, bge): Disable for sh2a-nofpu.
2004-02-20 Fred Fish <fnf@redhat.com>,
Corinna Vinschen <vinschen@redhat.com>
* config/sh/t-sh (MULTILIB_OPTIONS): Add 2a-nofpu.
(MULTILIB_EXCEPTIONS): Don't build littel-endian on sh2a.
2004-02-18 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (broken_move): Add support for movi20.
* config/sh/sh.h: Likewise.
(SHIFT_COUNT_TRUNCATED): Set for sh2a.
* config/sh/sh.md (udivsi3_sh2a): New.
(udivsi3): Call it.
(divsi3_sh2a): New.
(divsi3): Call it.
(mul_r): New.
(ashlsi3_sh2a): New.
(ashrsi3_sh2a): New.
(lshrsi3_sh2a): New.
(movsi_i): Disable for sh2a.
(movsi_ie): Add movi20.
(movsf_i, movsf_ie, movsf, ble, untyped_call): Explicitly enable
sh2a, for -m2a-nofpu mode.
2004-02-13 DJ Delorie <dj@redhat.com>
* config/sh/lib1funcs.asm: Handle double vs single better.
* config/sh/sh.h: Likewise.
2004-02-09 DJ Delorie <dj@redhat.com>
* config/sh/crt1.asm: Add support for sh2a.
* config/sh/elf.h: Likewise.
* config/sh/lib1funcs.asm: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/t-sh: Likewise.
From-SVN: r85286
2004-07-29 06:10:03 +00:00
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#if defined(__SH4__) || defined (__SH2A_DOUBLE__)
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Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
swap.w r0,r3
|
|
|
|
|
mov.l r3,@(4,r1)
|
2003-01-24 15:45:53 +00:00
|
|
|
#else /* defined (__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE*__) */
|
1998-10-02 08:22:31 +00:00
|
|
|
swap.w r0,r2
|
|
|
|
|
mov.l r2,@r1
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
#endif
|
|
|
|
|
#ifndef FMOVD_WORKS
|
1998-10-02 08:22:31 +00:00
|
|
|
xor #8,r0
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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|
|
#else
|
|
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xor #24,r0
|
|
|
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|
#endif
|
Introduce sh2a support.
2004-07-29 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Build multilibs for sh2a and sh2a-single by
default.
* config/sh/sh.h (SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Define by
default. Split their tests out of the corresponding SH4
multilibs.
* config/sh/t-sh (MULTILIB_MATCHES): Don't ever use SH4 or SH4a
multilibs for SH2a.
2004-07-28 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Handle sh2a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh2a command line flags.
* config/sh/t-mlib-sh2a: New.
* config/sh/t-mlib-sh2a-nofpu: New.
* config/sh/t-mlib-sh2a-single: New.
* config/sh/t-mlib-sh2a-single-only: New.
2004-07-09 Nick Clifton <nickc@redhat.com>
Issue 43400
* config/sh/sh.h (DRIVER_SELF_SPECS): Issue an error message if
-ml and -m2a are used together.
2004-03-23 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (sh_builtin_saveregs): Use the double code only
when we have a double-sized FPU.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/lib1funcs.asm (set_fpscr): Don't build if __SH2A_NOFPU__
is set.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Add cases for -msh2a-nofpu,
-msh2a-single and -msh2a-single-only
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/crt1.asm: Don't generate FPU instructions if __SH2A_NOFPU__
is set.
2004-02-20 DJ Delorie <dj@delorie.com>
* config/sh/sh.md (movsf_i, movsf_ie, movsf, ble, bge): Disable for sh2a-nofpu.
2004-02-20 Fred Fish <fnf@redhat.com>,
Corinna Vinschen <vinschen@redhat.com>
* config/sh/t-sh (MULTILIB_OPTIONS): Add 2a-nofpu.
(MULTILIB_EXCEPTIONS): Don't build littel-endian on sh2a.
2004-02-18 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (broken_move): Add support for movi20.
* config/sh/sh.h: Likewise.
(SHIFT_COUNT_TRUNCATED): Set for sh2a.
* config/sh/sh.md (udivsi3_sh2a): New.
(udivsi3): Call it.
(divsi3_sh2a): New.
(divsi3): Call it.
(mul_r): New.
(ashlsi3_sh2a): New.
(ashrsi3_sh2a): New.
(lshrsi3_sh2a): New.
(movsi_i): Disable for sh2a.
(movsi_ie): Add movi20.
(movsf_i, movsf_ie, movsf, ble, untyped_call): Explicitly enable
sh2a, for -m2a-nofpu mode.
2004-02-13 DJ Delorie <dj@redhat.com>
* config/sh/lib1funcs.asm: Handle double vs single better.
* config/sh/sh.h: Likewise.
2004-02-09 DJ Delorie <dj@redhat.com>
* config/sh/crt1.asm: Add support for sh2a.
* config/sh/elf.h: Likewise.
* config/sh/lib1funcs.asm: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/t-sh: Likewise.
From-SVN: r85286
2004-07-29 06:10:03 +00:00
|
|
|
#if defined(__SH4__) || defined (__SH2A_DOUBLE__)
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
|
|
|
swap.w r0,r2
|
|
|
|
|
rts
|
|
|
|
|
mov.l r2,@r1
|
2003-01-24 15:45:53 +00:00
|
|
|
#else /* defined(__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE*__) */
|
1998-10-02 08:22:31 +00:00
|
|
|
swap.w r0,r3
|
|
|
|
|
rts
|
|
|
|
|
mov.l r3,@(4,r1)
|
Add SH4 support:
* config/sh/lib1funcs.asm (___movstr_i4_even, ___movstr_i4_odd): Define.
(___movstrSI12_i4, ___sdivsi3_i4, ___udivsi3_i4): Define.
* sh.c (reg_class_from_letter, regno_reg_class): Add DF_REGS.
(fp_reg_names, assembler_dialect): New variables.
(print_operand_address): Handle SUBREGs.
(print_operand): Added 'o' case.
Don't use adj_offsettable_operand on PRE_DEC / POST_INC.
Name of FP registers depends on mode.
(expand_block_move): Emit different code for SH4 hardware.
(prepare_scc_operands): Use emit_sf_insn / emit_df_insn as appropriate.
(from_compare): Likewise.
(add_constant): New argument last_value. Changed all callers.
(find_barrier): Don't try HImode load for FPUL_REG.
(machine_dependent_reorg): Likewise.
(sfunc_uses_reg): A CLOBBER cannot be the address register use.
(gen_far_branch): Emit a barrier after the new jump.
(barrier_align): Don't trust instruction lengths before
fixing up pcloads.
(machine_dependent_reorg): Add support for FIRST_XD_REG .. LAST_XD_REG.
Use auto-inc addressing for fp registers if doubles need to
be loaded in two steps.
Set sh_flag_remove_dead_before_cse.
(push): Support for TARGET_FMOVD. Use gen_push_fpul for fpul.
(pop): Support for TARGET_FMOVD. Use gen_pop_fpul for fpul.
(calc_live_regs): Support for TARGET_FMOVD. Don't save FPSCR.
Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_prologue): Support for FIRST_XD_REG .. LAST_XD_REG.
(sh_expand_epilogue): Likewise.
(sh_builtin_saveregs): Use DFmode moves for fp regs on SH4.
(initial_elimination_offset): Take TARGET_ALIGN_DOUBLE into account.
(arith_reg_operand): FPUL_REG is OK for SH4.
(fp_arith_reg_operand, fp_extended_operand) New functions.
(tertiary_reload_operand, fpscr_operand): Likewise.
(commutative_float_operator, noncommutative_float_operator): Likewise.
(binary_float_operator, get_fpscr_rtx, emit_sf_insn): Likewise.
(emit_df_insn, expand_sf_unop, expand_sf_binop): Likewise.
(expand_df_unop, expand_df_binop, expand_fp_branch): Likewise.
(emit_fpscr_use, mark_use, remove_dead_before_cse): Likewise.
* sh.h (CPP_SPEC): Add support for -m4, m4-single, m4-single-only.
(CONDITIONAL_REGISTER_USAGE): Likewise.
(HARD_SH4_BIT, FPU_SINGLE_BIT, SH4_BIT, FMOVD_BIT): Define.
(TARGET_CACHE32, TARGET_SUPERSCALAR, TARGET_HARWARD): Define.
(TARGET_HARD_SH4, TARGET_FPU_SINGLE, TARGET_SH4, TARGET_FMOVD): Define.
(target_flag): Add -m4, m4-single, m4-single-only, -mfmovd.
(OPTIMIZATION_OPTIONS): If optimizing, set flag_omit_frame_pointer
to -1 and sh_flag_remove_dead_before_cse to 1.
(ASSEMBLER_DIALECT): Define to assembler_dialect.
(assembler_dialect, fp_reg_names): Declare.
(OVERRIDE_OPTIONS): Add code for TARGET_SH4.
Hide names of registers that are not accessible.
(CACHE_LOG): Take TARGET_CACHE32 into account.
(LOOP_ALIGN): Take TARGET_HARWARD into account.
(FIRST_XD_REG, LAST_XD_REG, FPSCR_REG): Define.
(FIRST_PSEUDO_REGISTER: Now 49.
(FIXED_REGISTERS, CALL_USED_REGISTERS): Include values for registers.
(HARD_REGNO_NREGS): Special treatment of FIRST_XD_REG .. LAST_XD_REG.
(HARD_REGNO_MODE_OK): Update.
(enum reg_class): Add DF_REGS and FPSCR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REG_ALLOC_ORDER): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Update.
(CLASS_CANNOT_CHANGE_SIZE, DEBUG_REGISTER_NAMES): Define.
(NPARM_REGS): Eight floating point parameter registers on SH4.
(BASE_RETURN_VALUE_REG): SH4 also passes double values
in floating point registers.
(GET_SH_ARG_CLASS) Likewise.
Complex float types are also returned in float registers.
(BASE_ARG_REG): Complex float types are also passes in float registers.
(FUNCTION_VALUE): Change mode like PROMOTE_MODE does.
(LIBCALL_VALUE): Remove trailing semicolon.
(ROUND_REG): Round when double precision value is passed in floating
point register(s).
(FUNCTION_ARG_ADVANCE): No change wanted for SH4 when things are
passed on the stack.
(FUNCTION_ARG): Little endian adjustment for SH4 SFmode.
(FUNCTION_ARG_PARTIAL_NREGS): Zero for SH4.
(TRAMPOLINE_ALIGNMENT): Take TARGET_HARWARD into account.
(INITIALIZE_TRAMPOLINE): Emit ic_invalidate_line for TARGET_HARWARD.
(MODE_DISP_OK_8): Not for SH4 DFmode.
(GO_IF_LEGITIMATE_ADDRESS): No base reg + index reg for SH4 DFmode.
Allow indexed addressing for PSImode after reload.
(LEGITIMIZE_ADDRESS): Not for SH4 DFmode.
(LEGITIMIZE_RELOAD_ADDRESS): Handle SH3E SFmode.
Don't change SH4 DFmode nor PSImode RELOAD_FOR_INPUT_ADDRESS.
(DOUBLE_TYPE_SIZE): 64 for SH4.
(RTX_COSTS): Add PLUS case.
Increae cost of ASHIFT, ASHIFTRT, LSHIFTRT case.
(REGISTER_MOVE_COST): Add handling of R0_REGS, FPUL_REGS, T_REGS,
MAC_REGS, PR_REGS, DF_REGS.
(REGISTER_NAMES): Use fp_reg_names.
(enum processor_type): Add PROCESSOR_SH4.
(sh_flag_remove_dead_before_cse): Declare.
(rtx_equal_function_value_matters, fpscr_rtx, get_fpscr_rtx): Declare.
(PREDICATE_CODES): Add binary_float_operator,
commutative_float_operator, fp_arith_reg_operand, fp_extended_operand,
fpscr_operand, noncommutative_float_operator.
(ADJUST_COST): Use different scale for TARGET_SUPERSCALAR.
(SH_DYNAMIC_SHIFT_COST): Cheaper for SH4.
* sh.md (attribute cpu): Add value sh4.
(attrbutes fmovd, issues): Define.
(attribute type): Add values dfp_arith, dfp_cmp, dfp_conv, dfdiv.
(function units memory, int, mpy, fp): Make dependent on issue rate.
(function units issue, single_issue, load_si, load): Define.
(function units load_store, fdiv, gp_fpul): Define.
(attribute hit_stack): Provide proper default.
(use_sfunc_addr+1, udivsi3): Predicated on ! TARGET_SH4.
(udivsi3_i4, udivsi3_i4_single, divsi3_i4, divsi3_i4_single): New insns.
(udivsi3, divsi3): Emit special patterns for SH4 hardware,
(mulsi3_call): Now uses match_operand for function address.
(mulsi3): Also emit code for SH1 case. Wrap result in REG_LIBCALL /
REG_RETVAL notes.
(push, pop, push_e, pop_e): Now define_expands.
(push_fpul, push_4, pop_fpul, pop_4, ic_invalidate_line): New expanders.
(movsi_ie): Added y/i alternative.
(ic_invalidate_line_i, movdf_i4): New insns.
(movdf_i4+[123], reload_outdf+[12345], movsi_y+[12]): New splitters.
(reload_indf, reload_outdf, reload_outsf, reload_insi): New expanders.
(movdf): Add special code for SH4.
(movsf_ie, movsf_ie+1, reload_insf, calli): Make use of fpscr visible.
(call_valuei, calli, call_value): Likewise.
(movsf): Emit no-op move.
(mov_nop, movsi_y): New insns.
(blt, sge): generalize to handle DFmode.
(return predicate): Call emit_fpscr_use and remove_dead_before_cse.
(block_move_real, block_lump_real): Predicate on ! TARGET_HARD_SH4.
(block_move_real_i4, block_lump_real_i4, fpu_switch): New insns.
(fpu_switch0, fpu_switch1, movpsi): New expanders.
(fpu_switch+[12], fix_truncsfsi2_i4_2+1): New splitters.
(toggle_sz): New insn.
(addsf3, subsf3, mulsf3, divsf3): Now define_expands.
(addsf3_i, subsf3_i, mulsf3_i4, mulsf3_ie, divsf3_i): New insns.
(macsf3): Make use of fpscr visible. Disable for SH4.
(floatsisf2): Make use of fpscr visible.
(floatsisf2_i4): New insn.
(floatsisf2_ie, fixsfsi, cmpgtsf_t, cmpeqsf_t): Disable for SH4.
(ieee_ccmpeqsf_t): Likewise.
(fix_truncsfsi2): Emit different code for SH4.
(fix_truncsfsi2_i4, fix_truncsfsi2_i4_2, cmpgtsf_t_i4): New insns.
(cmpeqsf_t_i4, ieee_ccmpeqsf_t_4): New insns.
(negsf2, sqrtsf2, abssf2): Now expanders.
(adddf3, subdf3i, muldf2, divdf3, floatsidf2): New expanders.
(negsf2_i, sqrtsf2_i, abssf2_i, adddf3_i, subdf3_i): New insns.
(muldf3_i, divdf3_i, floatsidf2_i, fix_truncdfsi2_i): New insns.
(fix_truncdfsi2, cmpdf, negdf2, sqrtdf2, absdf2): New expanders.
(fix_truncdfsi2_i4, cmpgtdf_t, cmpeqdf_t, ieee_ccmpeqdf_t): New insns.
(fix_truncdfsi2_i4_2+1): New splitters.
(negdf2_i, sqrtdf2_i, absdf2_i, extendsfdf2_i4): New insns.
(extendsfdf2, truncdfsf2): New expanders.
(truncdfsf2_i4): New insn.
* t-sh (LIB1ASMFUNCS): Add _movstr_i4, _sdivsi3_i4, _udivsi3_i4.
(MULTILIB_OPTIONS): Add m4-single-only/m4-single/m4.
* float-sh.h: When testing for __SH3E__, also test for
__SH4_SINGLE_ONLY__ .
* va-sh.h (__va_freg): Define to float.
(__va_greg, __fa_freg, __gnuc_va_list, va_start):
Define for __SH4_SINGLE_ONLY__ like for __SH3E__ .
(__PASS_AS_FLOAT, __TARGET_SH4_P): Likewise.
(__PASS_AS_FLOAT): Use different definition for __SH4__ and
__SH4_SINGLE__.
(TARGET_SH4_P): Define.
(va_arg): Use it.
* sh.md (movdf_k, movsf_i): Tweak the condition so that
init_expr_once is satisfied about the existence of load / store insns.
* sh.md (movsi_i, movsi_ie, movsi_i_lowpart, movsf_i, movsf_ie):
change m constraint in source operand to mr / mf .
* va-sh.h (__va_arg_sh1): Use __asm instead of asm.
* (__VA_REEF): Define.
(__va_arg_sh1): Use it.
* va-sh.h (va_start, va_arg, va_copy): Add parenteses.
From-SVN: r23777
1998-11-23 08:50:42 +00:00
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|
#endif
|
1998-10-02 08:22:31 +00:00
|
|
|
.align 2
|
2003-08-12 01:25:07 +00:00
|
|
|
#ifdef __PIC__
|
2007-04-25 08:03:55 +00:00
|
|
|
#ifdef __vxworks
|
|
|
|
|
LOCAL(set_fpscr_L0_base):
|
|
|
|
|
.long ___GOTT_BASE__
|
|
|
|
|
LOCAL(set_fpscr_L0_index):
|
|
|
|
|
.long ___GOTT_INDEX__
|
|
|
|
|
#else
|
2003-08-12 01:25:07 +00:00
|
|
|
LOCAL(set_fpscr_L0):
|
|
|
|
|
.long _GLOBAL_OFFSET_TABLE_
|
2007-04-25 08:03:55 +00:00
|
|
|
#endif
|
2003-08-12 01:25:07 +00:00
|
|
|
LOCAL(set_fpscr_L1):
|
|
|
|
|
.long GLOBAL(fpscr_values@GOT)
|
|
|
|
|
#else
|
2000-08-16 21:17:40 +00:00
|
|
|
LOCAL(set_fpscr_L1):
|
|
|
|
|
.long GLOBAL(fpscr_values)
|
2003-08-12 01:25:07 +00:00
|
|
|
#endif
|
2002-12-16 18:23:00 +00:00
|
|
|
|
|
|
|
|
ENDFUNC(GLOBAL(set_fpscr))
|
2002-12-21 23:26:16 +00:00
|
|
|
#ifndef NO_FPSCR_VALUES
|
1998-10-02 08:22:31 +00:00
|
|
|
#ifdef __ELF__
|
2000-08-16 21:17:40 +00:00
|
|
|
.comm GLOBAL(fpscr_values),8,4
|
1998-10-02 08:22:31 +00:00
|
|
|
#else
|
2000-08-16 21:17:40 +00:00
|
|
|
.comm GLOBAL(fpscr_values),8
|
1998-10-02 08:22:31 +00:00
|
|
|
#endif /* ELF */
|
2002-12-21 23:26:16 +00:00
|
|
|
#endif /* NO_FPSCR_VALUES */
|
2003-01-24 15:45:53 +00:00
|
|
|
#endif /* SH2E / SH3E / SH4 */
|
Introduce sh2a support.
2004-07-29 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Build multilibs for sh2a and sh2a-single by
default.
* config/sh/sh.h (SUPPORT_SH2A, SUPPORT_SH2A_SINGLE): Define by
default. Split their tests out of the corresponding SH4
multilibs.
* config/sh/t-sh (MULTILIB_MATCHES): Don't ever use SH4 or SH4a
multilibs for SH2a.
2004-07-28 Alexandre Oliva <aoliva@redhat.com>
* config.gcc: Handle sh2a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh2a command line flags.
* config/sh/t-mlib-sh2a: New.
* config/sh/t-mlib-sh2a-nofpu: New.
* config/sh/t-mlib-sh2a-single: New.
* config/sh/t-mlib-sh2a-single-only: New.
2004-07-09 Nick Clifton <nickc@redhat.com>
Issue 43400
* config/sh/sh.h (DRIVER_SELF_SPECS): Issue an error message if
-ml and -m2a are used together.
2004-03-23 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (sh_builtin_saveregs): Use the double code only
when we have a double-sized FPU.
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/lib1funcs.asm (set_fpscr): Don't build if __SH2A_NOFPU__
is set.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Add cases for -msh2a-nofpu,
-msh2a-single and -msh2a-single-only
2004-02-24 Corinna Vinschen <vinschen@redhat.com>
* config/sh/crt1.asm: Don't generate FPU instructions if __SH2A_NOFPU__
is set.
2004-02-20 DJ Delorie <dj@delorie.com>
* config/sh/sh.md (movsf_i, movsf_ie, movsf, ble, bge): Disable for sh2a-nofpu.
2004-02-20 Fred Fish <fnf@redhat.com>,
Corinna Vinschen <vinschen@redhat.com>
* config/sh/t-sh (MULTILIB_OPTIONS): Add 2a-nofpu.
(MULTILIB_EXCEPTIONS): Don't build littel-endian on sh2a.
2004-02-18 DJ Delorie <dj@redhat.com>
* config/sh/sh.c (broken_move): Add support for movi20.
* config/sh/sh.h: Likewise.
(SHIFT_COUNT_TRUNCATED): Set for sh2a.
* config/sh/sh.md (udivsi3_sh2a): New.
(udivsi3): Call it.
(divsi3_sh2a): New.
(divsi3): Call it.
(mul_r): New.
(ashlsi3_sh2a): New.
(ashrsi3_sh2a): New.
(lshrsi3_sh2a): New.
(movsi_i): Disable for sh2a.
(movsi_ie): Add movi20.
(movsf_i, movsf_ie, movsf, ble, untyped_call): Explicitly enable
sh2a, for -m2a-nofpu mode.
2004-02-13 DJ Delorie <dj@redhat.com>
* config/sh/lib1funcs.asm: Handle double vs single better.
* config/sh/sh.h: Likewise.
2004-02-09 DJ Delorie <dj@redhat.com>
* config/sh/crt1.asm: Add support for sh2a.
* config/sh/elf.h: Likewise.
* config/sh/lib1funcs.asm: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/t-sh: Likewise.
From-SVN: r85286
2004-07-29 06:10:03 +00:00
|
|
|
#endif /* __SH2A_NOFPU__ */
|
1998-10-02 08:22:31 +00:00
|
|
|
#endif /* L_set_fpscr */
|
2000-09-07 04:38:34 +00:00
|
|
|
#ifdef L_ic_invalidate
|
2016-04-29 14:10:26 +00:00
|
|
|
|
|
|
|
|
#if defined(__SH4A__)
|
Introduce sh4a support.
gcc/ChangeLog:
Introduce sh4a support.
* config.gcc: Handle sh4a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh4a command line flags.
* config/sh/t-mlib-sh4a: New.
* config/sh/t-mlib-sh4al: New.
* config/sh/t-mlib-sh4a-nofpu: New.
* config/sh/t-mlib-sh4a-single: New.
* config/sh/t-mlib-sh4a-single-only: New.
2004-02-20 DJ Delorie <dj@redhat.com>
* config/sh/sh.md ("movua"): Change constraint from "m" to "Sua".
* config/sh/sh.h (EXTRA_CONSTRAINT_S): Add "Sua" support.
2003-08-22 Eric Christopher <echristo@redhat.com>
* config/sh/sh4a.md: Update for chip errata.
2003-08-07 Eric Christopher <echristo@redhat.com>
* config/sh/sh4a.md: New file. sh4a processor description.
2003-07-08 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (TARGET_SWITCHES): Added 4al. Adjust description
of -m4a-nofpu.
(SH_ASM_SPEC): Pass -dsp for -m4al, not -m4a-nofpu.
* config/sh/t-sh (MULTILIB_MATCHES): Map -m4al to -m4a-nofpu.
* doc/invoke.texi (SH Options): Document -m4al.
2003-07-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (expand_block_move): Remove commented-out code
checked in by mistake.
(sh_cannot_change_mode_class): Enable SUBREGs to be used to select
single elements from SFmode vectors.
* config/sh/sh.md (fsca): Use VEC_CONCAT to initialize the output
register.
(sinsf2, cossf2, sindf2, cosdf2): Don't emit CLOBBER.
2003-07-01 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): Remove variable declarations.
* config/sh/sh.c (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): New functions.
(sh_fsca_sf2int_rtx, sh_fsca_df2int_rtx,
sh_fsca_int2sf_rtx): New static variables.
* config/sh/sh-protos.h (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): Declare.
* config/sh/sh.md: Adjust.
* doc/invoke.texi (SH Options): Document new options.
* config/sh/lib1funcs.asm (ic_invalidate): Remove SH4a forward
compatibility from SH4 code.
2003-06-27 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (expand_block_move): Don't emit POST_INC too
early.
(memory_movsrc_operand): Renamed to...
(unaligned_load_operand): ... this. Simplified.
* config/sh/sh.h (PREDICATE_CODES): Adjust.
* config/sh/sh.md (movua, extv, extzv): Likewise. Change movua's
input operand to SImode, and adjust the others. Introduce
post-increment by peephole.
* config/sh/sh.c (expand_block_move): Give the target address the
same mode as the temp reg.
* config/sh/sh.c (expand_block_move): Use a temp reg for unaligned
copying.
2003-06-26 Alexandre Oliva <aoliva@redhat.com>
Introduce support for SH4a.
* config/sh/lib1funcs.asm (ic_invalidate): Use icbi if
__SH4A__. Emit 4 4kb blocks and touch all of them otherwise.
* config/sh/sh.c (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): New.
(sh_init_builtins): Initialize them.
(print_operand): Support `d'.
(expand_block_move): Use movua if src is misaligned.
(memory_movsrc_operand): New.
* config/sh/sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH4A__
and one of the SH4 macros.
(SH4A_BIT, TARGET_SH4A_ARCH, TARGET_SH4A_FP,
SELECT_SH4A_NOFPU, SELECT_SH4A_SINGLE_ONLY, SELECT_SH4A,
SELECT_SH4A_SINGLE): New.
(TARGET_NONE): Add SH4A_BIT.
(TARGET_SWITCHES): Add 4a-single-only, 4a-single, 4a-nofpu and 4a.
(SH_ASM_SPEC): Pass -dsp if -m4a-nofpu.
(sh_fsca_sf2int, sh_fsca_df2int, sh_fsca_int2sf): Declare.
(OVERRIDE_OPTIONS): Set cpu to CPU_SH4A when appropriate.
(enum processor_type): Added PROCESSOR_SH4A.
(PREDICATE_CODES): Add memory_movsrc_operand.
* config/sh/sh.md: Removed unused variables.
(attr cpu): Add sh4a.
(attr type): Add movua, fsrra and fsca.
(prefetch): New, for SH4.
(ic_invalidate_line, ic_invalidate_line_sh4a): Use icbi.
(toggle_sz): Set type to fp.
(toggle_pr, rsqrtsf2, fsca, sinsf2, cossf2, sindf2, cosdf2): New.
(movua, extv, extzv): New.
* config/sh/t-sh: Add multilibs for 4a, 4a-nofpu, 4a-single
and 4a-single-only.
gcc/testsuite/ChangeLog:
2003-07-06 Alexandre Oliva <aoliva@redhat.com>
* gcc.dg/sh4a-memmovua.c: Tweak regular expression.
2003-07-01 Alexandre Oliva <aoliva@redhat.com>
* gcc.dg/sh4a-bitmovua.c: New.
* gcc.dg/sh4a-cos.c: New.
* gcc.dg/sh4a-cosf.c: New.
* gcc.dg/sh4a-fprun.c: New.
* gcc.dg/sh4a-fsrra.c: New.
* gcc.dg/sh4a-memmovua.c: New.
* gcc.dg/sh4a-sin.c: New.
* gcc.dg/sh4a-sincos.c: New.
* gcc.dg/sh4a-sincosf.c: New.
* gcc.dg/sh4a-sinf.c: New.
libstdc++-v3/ChangeLog:
2003-10-01 Eric Christopher <echristo@redhat.com>
* config/cpu/sh/atomicity.h (__exchange_and_add): Remove 'm'
constraint.
2003-07-09 Alexandre Oliva <aoliva@redhat.com>
* config/cpu/sh/atomicity.h: New. Use movli and movco on SH4a.
From-SVN: r85257
2004-07-28 09:13:58 +00:00
|
|
|
.global GLOBAL(ic_invalidate)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
HIDDEN_FUNC(GLOBAL(ic_invalidate))
|
Introduce sh4a support.
gcc/ChangeLog:
Introduce sh4a support.
* config.gcc: Handle sh4a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh4a command line flags.
* config/sh/t-mlib-sh4a: New.
* config/sh/t-mlib-sh4al: New.
* config/sh/t-mlib-sh4a-nofpu: New.
* config/sh/t-mlib-sh4a-single: New.
* config/sh/t-mlib-sh4a-single-only: New.
2004-02-20 DJ Delorie <dj@redhat.com>
* config/sh/sh.md ("movua"): Change constraint from "m" to "Sua".
* config/sh/sh.h (EXTRA_CONSTRAINT_S): Add "Sua" support.
2003-08-22 Eric Christopher <echristo@redhat.com>
* config/sh/sh4a.md: Update for chip errata.
2003-08-07 Eric Christopher <echristo@redhat.com>
* config/sh/sh4a.md: New file. sh4a processor description.
2003-07-08 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (TARGET_SWITCHES): Added 4al. Adjust description
of -m4a-nofpu.
(SH_ASM_SPEC): Pass -dsp for -m4al, not -m4a-nofpu.
* config/sh/t-sh (MULTILIB_MATCHES): Map -m4al to -m4a-nofpu.
* doc/invoke.texi (SH Options): Document -m4al.
2003-07-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (expand_block_move): Remove commented-out code
checked in by mistake.
(sh_cannot_change_mode_class): Enable SUBREGs to be used to select
single elements from SFmode vectors.
* config/sh/sh.md (fsca): Use VEC_CONCAT to initialize the output
register.
(sinsf2, cossf2, sindf2, cosdf2): Don't emit CLOBBER.
2003-07-01 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): Remove variable declarations.
* config/sh/sh.c (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): New functions.
(sh_fsca_sf2int_rtx, sh_fsca_df2int_rtx,
sh_fsca_int2sf_rtx): New static variables.
* config/sh/sh-protos.h (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): Declare.
* config/sh/sh.md: Adjust.
* doc/invoke.texi (SH Options): Document new options.
* config/sh/lib1funcs.asm (ic_invalidate): Remove SH4a forward
compatibility from SH4 code.
2003-06-27 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (expand_block_move): Don't emit POST_INC too
early.
(memory_movsrc_operand): Renamed to...
(unaligned_load_operand): ... this. Simplified.
* config/sh/sh.h (PREDICATE_CODES): Adjust.
* config/sh/sh.md (movua, extv, extzv): Likewise. Change movua's
input operand to SImode, and adjust the others. Introduce
post-increment by peephole.
* config/sh/sh.c (expand_block_move): Give the target address the
same mode as the temp reg.
* config/sh/sh.c (expand_block_move): Use a temp reg for unaligned
copying.
2003-06-26 Alexandre Oliva <aoliva@redhat.com>
Introduce support for SH4a.
* config/sh/lib1funcs.asm (ic_invalidate): Use icbi if
__SH4A__. Emit 4 4kb blocks and touch all of them otherwise.
* config/sh/sh.c (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): New.
(sh_init_builtins): Initialize them.
(print_operand): Support `d'.
(expand_block_move): Use movua if src is misaligned.
(memory_movsrc_operand): New.
* config/sh/sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH4A__
and one of the SH4 macros.
(SH4A_BIT, TARGET_SH4A_ARCH, TARGET_SH4A_FP,
SELECT_SH4A_NOFPU, SELECT_SH4A_SINGLE_ONLY, SELECT_SH4A,
SELECT_SH4A_SINGLE): New.
(TARGET_NONE): Add SH4A_BIT.
(TARGET_SWITCHES): Add 4a-single-only, 4a-single, 4a-nofpu and 4a.
(SH_ASM_SPEC): Pass -dsp if -m4a-nofpu.
(sh_fsca_sf2int, sh_fsca_df2int, sh_fsca_int2sf): Declare.
(OVERRIDE_OPTIONS): Set cpu to CPU_SH4A when appropriate.
(enum processor_type): Added PROCESSOR_SH4A.
(PREDICATE_CODES): Add memory_movsrc_operand.
* config/sh/sh.md: Removed unused variables.
(attr cpu): Add sh4a.
(attr type): Add movua, fsrra and fsca.
(prefetch): New, for SH4.
(ic_invalidate_line, ic_invalidate_line_sh4a): Use icbi.
(toggle_sz): Set type to fp.
(toggle_pr, rsqrtsf2, fsca, sinsf2, cossf2, sindf2, cosdf2): New.
(movua, extv, extzv): New.
* config/sh/t-sh: Add multilibs for 4a, 4a-nofpu, 4a-single
and 4a-single-only.
gcc/testsuite/ChangeLog:
2003-07-06 Alexandre Oliva <aoliva@redhat.com>
* gcc.dg/sh4a-memmovua.c: Tweak regular expression.
2003-07-01 Alexandre Oliva <aoliva@redhat.com>
* gcc.dg/sh4a-bitmovua.c: New.
* gcc.dg/sh4a-cos.c: New.
* gcc.dg/sh4a-cosf.c: New.
* gcc.dg/sh4a-fprun.c: New.
* gcc.dg/sh4a-fsrra.c: New.
* gcc.dg/sh4a-memmovua.c: New.
* gcc.dg/sh4a-sin.c: New.
* gcc.dg/sh4a-sincos.c: New.
* gcc.dg/sh4a-sincosf.c: New.
* gcc.dg/sh4a-sinf.c: New.
libstdc++-v3/ChangeLog:
2003-10-01 Eric Christopher <echristo@redhat.com>
* config/cpu/sh/atomicity.h (__exchange_and_add): Remove 'm'
constraint.
2003-07-09 Alexandre Oliva <aoliva@redhat.com>
* config/cpu/sh/atomicity.h: New. Use movli and movco on SH4a.
From-SVN: r85257
2004-07-28 09:13:58 +00:00
|
|
|
GLOBAL(ic_invalidate):
|
|
|
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ocbwb @r4
|
|
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synco
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icbi @r4
|
2009-04-06 11:22:09 +00:00
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rts
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nop
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Introduce sh4a support.
gcc/ChangeLog:
Introduce sh4a support.
* config.gcc: Handle sh4a multilibs and cpu selection.
* config/sh/sh.h: Likewise. Handle sh4a command line flags.
* config/sh/t-mlib-sh4a: New.
* config/sh/t-mlib-sh4al: New.
* config/sh/t-mlib-sh4a-nofpu: New.
* config/sh/t-mlib-sh4a-single: New.
* config/sh/t-mlib-sh4a-single-only: New.
2004-02-20 DJ Delorie <dj@redhat.com>
* config/sh/sh.md ("movua"): Change constraint from "m" to "Sua".
* config/sh/sh.h (EXTRA_CONSTRAINT_S): Add "Sua" support.
2003-08-22 Eric Christopher <echristo@redhat.com>
* config/sh/sh4a.md: Update for chip errata.
2003-08-07 Eric Christopher <echristo@redhat.com>
* config/sh/sh4a.md: New file. sh4a processor description.
2003-07-08 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (TARGET_SWITCHES): Added 4al. Adjust description
of -m4a-nofpu.
(SH_ASM_SPEC): Pass -dsp for -m4al, not -m4a-nofpu.
* config/sh/t-sh (MULTILIB_MATCHES): Map -m4al to -m4a-nofpu.
* doc/invoke.texi (SH Options): Document -m4al.
2003-07-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (expand_block_move): Remove commented-out code
checked in by mistake.
(sh_cannot_change_mode_class): Enable SUBREGs to be used to select
single elements from SFmode vectors.
* config/sh/sh.md (fsca): Use VEC_CONCAT to initialize the output
register.
(sinsf2, cossf2, sindf2, cosdf2): Don't emit CLOBBER.
2003-07-01 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): Remove variable declarations.
* config/sh/sh.c (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): New functions.
(sh_fsca_sf2int_rtx, sh_fsca_df2int_rtx,
sh_fsca_int2sf_rtx): New static variables.
* config/sh/sh-protos.h (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): Declare.
* config/sh/sh.md: Adjust.
* doc/invoke.texi (SH Options): Document new options.
* config/sh/lib1funcs.asm (ic_invalidate): Remove SH4a forward
compatibility from SH4 code.
2003-06-27 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (expand_block_move): Don't emit POST_INC too
early.
(memory_movsrc_operand): Renamed to...
(unaligned_load_operand): ... this. Simplified.
* config/sh/sh.h (PREDICATE_CODES): Adjust.
* config/sh/sh.md (movua, extv, extzv): Likewise. Change movua's
input operand to SImode, and adjust the others. Introduce
post-increment by peephole.
* config/sh/sh.c (expand_block_move): Give the target address the
same mode as the temp reg.
* config/sh/sh.c (expand_block_move): Use a temp reg for unaligned
copying.
2003-06-26 Alexandre Oliva <aoliva@redhat.com>
Introduce support for SH4a.
* config/sh/lib1funcs.asm (ic_invalidate): Use icbi if
__SH4A__. Emit 4 4kb blocks and touch all of them otherwise.
* config/sh/sh.c (sh_fsca_sf2int, sh_fsca_df2int,
sh_fsca_int2sf): New.
(sh_init_builtins): Initialize them.
(print_operand): Support `d'.
(expand_block_move): Use movua if src is misaligned.
(memory_movsrc_operand): New.
* config/sh/sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH4A__
and one of the SH4 macros.
(SH4A_BIT, TARGET_SH4A_ARCH, TARGET_SH4A_FP,
SELECT_SH4A_NOFPU, SELECT_SH4A_SINGLE_ONLY, SELECT_SH4A,
SELECT_SH4A_SINGLE): New.
(TARGET_NONE): Add SH4A_BIT.
(TARGET_SWITCHES): Add 4a-single-only, 4a-single, 4a-nofpu and 4a.
(SH_ASM_SPEC): Pass -dsp if -m4a-nofpu.
(sh_fsca_sf2int, sh_fsca_df2int, sh_fsca_int2sf): Declare.
(OVERRIDE_OPTIONS): Set cpu to CPU_SH4A when appropriate.
(enum processor_type): Added PROCESSOR_SH4A.
(PREDICATE_CODES): Add memory_movsrc_operand.
* config/sh/sh.md: Removed unused variables.
(attr cpu): Add sh4a.
(attr type): Add movua, fsrra and fsca.
(prefetch): New, for SH4.
(ic_invalidate_line, ic_invalidate_line_sh4a): Use icbi.
(toggle_sz): Set type to fp.
(toggle_pr, rsqrtsf2, fsca, sinsf2, cossf2, sindf2, cosdf2): New.
(movua, extv, extzv): New.
* config/sh/t-sh: Add multilibs for 4a, 4a-nofpu, 4a-single
and 4a-single-only.
gcc/testsuite/ChangeLog:
2003-07-06 Alexandre Oliva <aoliva@redhat.com>
* gcc.dg/sh4a-memmovua.c: Tweak regular expression.
2003-07-01 Alexandre Oliva <aoliva@redhat.com>
* gcc.dg/sh4a-bitmovua.c: New.
* gcc.dg/sh4a-cos.c: New.
* gcc.dg/sh4a-cosf.c: New.
* gcc.dg/sh4a-fprun.c: New.
* gcc.dg/sh4a-fsrra.c: New.
* gcc.dg/sh4a-memmovua.c: New.
* gcc.dg/sh4a-sin.c: New.
* gcc.dg/sh4a-sincos.c: New.
* gcc.dg/sh4a-sincosf.c: New.
* gcc.dg/sh4a-sinf.c: New.
libstdc++-v3/ChangeLog:
2003-10-01 Eric Christopher <echristo@redhat.com>
* config/cpu/sh/atomicity.h (__exchange_and_add): Remove 'm'
constraint.
2003-07-09 Alexandre Oliva <aoliva@redhat.com>
* config/cpu/sh/atomicity.h: New. Use movli and movco on SH4a.
From-SVN: r85257
2004-07-28 09:13:58 +00:00
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ENDFUNC(GLOBAL(ic_invalidate))
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2016-04-29 14:10:26 +00:00
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#elif defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || defined(__SH4_NOFPU__)
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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/* For system code, we use ic_invalidate_line_i, but user code
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needs a different mechanism. A kernel call is generally not
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available, and it would also be slow. Different SH4 variants use
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different sizes and associativities of the Icache. We use a small
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bit of dispatch code that can be put hidden in every shared object,
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which calls the actual processor-specific invalidation code in a
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separate module.
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Or if you have operating system support, the OS could mmap the
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procesor-specific code from a single page, since it is highly
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repetitive. */
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2000-09-07 04:38:34 +00:00
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.global GLOBAL(ic_invalidate)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
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|
HIDDEN_FUNC(GLOBAL(ic_invalidate))
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2000-09-07 04:38:34 +00:00
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GLOBAL(ic_invalidate):
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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#ifdef __pic__
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2007-04-25 08:03:55 +00:00
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#ifdef __vxworks
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mov.l 1f,r1
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mov.l 2f,r0
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mov.l @r1,r1
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mov.l 0f,r2
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mov.l @(r0,r1),r0
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#else
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mov.l 1f,r1
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mova 1f,r0
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mov.l 0f,r2
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
add r1,r0
|
2007-04-25 08:03:55 +00:00
|
|
|
#endif
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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|
mov.l @(r0,r2),r1
|
2007-04-25 08:03:55 +00:00
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#else
|
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mov.l 0f,r1
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
#endif
|
|
|
|
|
ocbwb @r4
|
|
|
|
|
mov.l @(8,r1),r0
|
|
|
|
|
sub r1,r4
|
|
|
|
|
and r4,r0
|
|
|
|
|
add r1,r0
|
|
|
|
|
jmp @r0
|
|
|
|
|
mov.l @(4,r1),r0
|
2007-07-04 10:14:28 +00:00
|
|
|
.align 2
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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#ifndef __pic__
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0: .long GLOBAL(ic_invalidate_array)
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#else /* __pic__ */
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.global GLOBAL(ic_invalidate_array)
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2007-04-25 08:03:55 +00:00
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0: .long GLOBAL(ic_invalidate_array)@GOT
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#ifdef __vxworks
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#else
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#endif
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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ENDFUNC(GLOBAL(ic_invalidate))
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#endif /* __pic__ */
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#endif /* SH4 */
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#endif /* L_ic_invalidate */
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#ifdef L_ic_invalidate_array
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2016-04-29 14:10:26 +00:00
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#if defined(__SH4A__) || (defined (__FORCE_SH4A__) && (defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || defined(__SH4_NOFPU__)))
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2006-03-27 14:11:14 +00:00
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.global GLOBAL(ic_invalidate_array)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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/* This is needed when an SH4 dso with trampolines is used on SH4A. */
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.global GLOBAL(ic_invalidate_array)
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FUNC(GLOBAL(ic_invalidate_array))
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GLOBAL(ic_invalidate_array):
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add r1,r4
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synco
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icbi @r4
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2009-04-06 11:22:09 +00:00
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rts
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nop
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.align 2
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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.long 0
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ENDFUNC(GLOBAL(ic_invalidate_array))
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2016-04-29 14:10:26 +00:00
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#elif defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || defined(__SH4_NOFPU__)
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
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|
.global GLOBAL(ic_invalidate_array)
|
2001-06-03 22:08:26 +00:00
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.p2align 5
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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FUNC(GLOBAL(ic_invalidate_array))
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2001-06-03 22:08:26 +00:00
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/* This must be aligned to the beginning of a cache line. */
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
GLOBAL(ic_invalidate_array):
|
|
|
|
|
#ifndef WAYS
|
|
|
|
|
#define WAYS 4
|
|
|
|
|
#define WAY_SIZE 0x4000
|
|
|
|
|
#endif
|
|
|
|
|
#if WAYS == 1
|
|
|
|
|
.rept WAY_SIZE * WAYS / 32
|
|
|
|
|
rts
|
|
|
|
|
nop
|
|
|
|
|
.rept 7
|
|
|
|
|
.long WAY_SIZE - 32
|
|
|
|
|
.endr
|
|
|
|
|
.endr
|
|
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|
|
#elif WAYS <= 6
|
|
|
|
|
.rept WAY_SIZE * WAYS / 32
|
|
|
|
|
braf r0
|
|
|
|
|
add #-8,r0
|
|
|
|
|
.long WAY_SIZE + 8
|
|
|
|
|
.long WAY_SIZE - 32
|
|
|
|
|
.rept WAYS-2
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braf r0
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nop
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|
.endr
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|
|
.rept 7 - WAYS
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rts
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|
|
|
|
nop
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|
.endr
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|
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.endr
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#else /* WAYS > 6 */
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|
/* This variant needs two different pages for mmap-ing. */
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.rept WAYS-1
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.rept WAY_SIZE / 32
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braf r0
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nop
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.long WAY_SIZE
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.rept 6
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.long WAY_SIZE - 32
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.endr
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.endr
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.endr
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.rept WAY_SIZE / 32
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2000-09-07 04:38:34 +00:00
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rts
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2001-06-03 22:08:26 +00:00
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.rept 15
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2000-09-07 04:38:34 +00:00
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nop
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.endr
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2001-06-03 22:08:26 +00:00
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.endr
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
#endif /* WAYS */
|
|
|
|
|
ENDFUNC(GLOBAL(ic_invalidate_array))
|
2000-09-07 04:38:34 +00:00
|
|
|
#endif /* SH4 */
|
re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
|
|
|
#endif /* L_ic_invalidate_array */
|
Contribute sh64-elf.
2002-02-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (TARGET_CANNOT_MODIFY_JUMPS_P): Define to...
(sh_cannot_modify_jumps_p): New function.
2002-02-05 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (TARGET_MS_BITFIELD_LAYOUT_P): Define to...
(sh_ms_bitfield_layout_p): New function.
2002-02-04 Alexandre Oliva <aoliva@redhat.com>
Zack Weinberg <zack@codesourcery.com>
* config/sh/sh.h (TRAMPOLINE_ADJUST_ADDRESS): Use
expand_simple_binop instead of expand_binop.
2002-02-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (OVERRIDE_OPTIONS) [! TARGET_SH5]: Disable
use of .quad and .uaquad.
* config/sh/sh.c (TARGET_ASM_UNALIGNED_DI_OP,
TARGET_ASM_ALIGNED_DI_OP): Add comment pointing to the above.
2002-01-24 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (movdi_const, movdi_const_32bit,
movdi_const_16bit): Make sure all CONSTs have modes.
(sym2PIC): Ditto, but by adjusting all callers.
* config/sh/sh.c (calc_live_regs) [TARGET_SHCOMPACT]: Set pr_live
if the prologue calls the SHmedia argument decoder or register
saver.
2002-01-24 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (TARGET_ASM_UNALIGNED_DI_OP): Define.
(TARGET_ASM_ALIGNED_DI_OP): Likewise.
(sh_expand_epilogue): Don't emit USE of return target register.
(prepare_move_operands): Legitimize DImode PIC addresses.
(sh_media_register_for_return): Skip tr0, used to initialize the
PIC register.
(sh_expand_prologue): Remove explicit USE of return register.
(nonpic_symbol_mentioned_p): PC is non-PIC. Don't recurse in
CONST_DOUBLEs. UNSPEC_GOTPLT is PIC.
* config/sh/sh.h (ASM_OUTPUT_DOUBLE_INT): Removed, obsolete.
(OVERRIDE_OPTIONS): Don't disable PIC on SH5.
(EXTRA_CONSTRAINT_S): Use MOVI_SHORI_BASE_OPERAND_P instead of
EXTRA_CONSTRAINT_T.
(GOT_ENTRY_P, GOTPLT_ENTRY_P, GOTOFF_P, PIC_ADDR_P): New.
(MOVI_SHORI_BASE_OPERAND_P): New.
(NON_PIC_REFERENCE_P, PIC_REFERENCE_P): New.
(EXTRA_CONSTRAINT_T): Define in terms of them.
(OUTPUT_ADDR_CONST_EXTRA): Handle UNSPEC_GOTPLT.
* config/sh/sh.md (movsi_media, movsi_media_nofpu,
movdi_media, movdi_media_nofpu): Add SIBCALL_REGS class to
alternatives supporting TARGET_REGS.
(UNSPEC_GOTPLT): New constant.
(movdi split): Move incrementing of LABEL_NUSES...
(movdi_const, movdi_const_32bit): Here. Use
MOVI_SHORI_BASE_OPERAND_P instead of EXTRA_CONSTRAINT_T.
(movdi_const_16bit): New.
(call, call_value) [flag_pic]: Use GOTPLT.
(call_pop, call_value_pop): New expands.
(call_pop_compact, call_pop_rettramp): New insns.
(call_value_pop_compact, call_value_pop_rettramp): New insns.
(sibcall) [flag_pic]: Use GOT.
(builtint_setjmp_receiver): Remove bogus, unused expand.
(GOTaddr2picreg): Implement for SHcompact and SHmedia.
(*pt, *ptb, ptrel): New insns.
(sym2GOT): Handle DImode GOT.
(sym2GOTPLT, symGOTPLT2reg): New expands.
(sym2PIC): New expand.
(shcompact_return_tramp): Use GOTPLT to return trampoline.
(shcompact_return_tramp_i): Use return register explicitly.
* config/sh/sh.h (OVERRIDE_OPTIONS) [TARGET_SHMEDIA]: Don't
disable flag_reorder_blocks.
2002-01-19 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (sibcall_compact): Reorder return, uses and
clobbers, for clarity.
(sibcall_epilogue) [TARGET_SHCOMPACT]: Mark saving and
restoring of r0 in macl as MAYBE_DEAD.
2002-01-18 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (LONG_DOUBLE_TYPE_SIZE): Define.
* config/sh/sh.md (movv4sf_i, movv16sf_i): Fix uses of
alter_subreg all over.
(jump) [TARGET_SHMEDIA]: FAIL to create new jumps after
reload, instead of emitting instructions that would require
reloading.
(casesi_load_media): Add missing modes.
2001-11-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (sh_expand_prologue): Mark the PIC register
as used if the argument decoder is called.
2001-08-28 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (udivsi3, divsi3): Load libcall symbol name in
Pmode, then extend it to DImode if necessary.
2001-08-28 Stephen Clarke <Stephen.Clarke@st.com>
* config/sh/sh.h (LEGITIMATE_CONSTANT_P): Don't accept DFmode
constants in FPU-enabled SHmedia, let them be loaded from memory.
2001-08-28 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (cmpeqdi_media, cmpgtdi_media, cmpgtudi_media):
Adjust whitespace in assembly output templates.
2001-08-28 Stephen Clarke <Stephen.Clarke@st.com>
* config/sh/sh.md (movdicc_false, movdicc_true, movdicc): Adjust
mode of if_then_else.
2001-08-04 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh64.h (CPP_DEFAULT_CPU_SPEC): Override definition in
sh.h.
2001-07-26 Andrew Haley <aph@cambridge.redhat.com>
Joern Rennecke <amylaar@redhat.com>
* config/sh/sh64.h (CPP_DEFAULT_CPU_SPEC): New.
(SUBTARGET_CPP_PTR_SPEC): New.
(SUBTARGET_CPP_SPEC): Remove.
2001-07-06 Chandrakala Chavva <cchavva@redhat.com>
* config/sh/sh.md (movsf_media_nofpu+1, movdf_media_nofpu+1):
Fix typo in previous checkin.
2001-07-11 Chandrakala Chavva <cchavva@redhat.com>
* config/sh/sh.h (MODES_TIEABLE_P): Fix redact indentations.
2001-07-10 Chandrakala Chavva <cchavva@cygnus.com>
Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (MODES_TIEABLE_P): Don't tie modes wider than
what single FP register can hold for SHmedia target.
2001-07-06 Chandrakala Chavva <cchavva@redhat.com>
Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (movsf_media_nofpu+1, movdf_media_nofpu+1):
Do not split into SUBREG.
2001-06-14 Alexandre Oliva <aoliva@redhat.com>
* config/sh/ushmedia.h, config/sh/sshmedia.h: Updated signatures
and added new functions as specified in SH5 ABI r9.
2001-06-04 Alexandre Oliva <aoliva@redhat.com>
* config/sh/lib1funcs.asm (GCC_nested_trampoline): Align to an
8-byte boundary.
2001-06-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (dump_table): Add const0_rtx in calls of
gen_consttable_4 and gen_consttable_8. Emit multiple labels
and consttable_window_ends.
2001-06-03 Graham Stott <grahams@redhat,com>
* config/sh/sh.md (movdi split): Remove unused variable last_insn.
2001-05-16 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (print_operand): Handle floating-point pair,
vector and matrix registers.
* config/sh/sh.h (REGISTER_MOVE_COST): Take floating-pointer
vector modes into account.
* config/sh/sh.md (movv2sf): Split move between registers into
movdf.
(movv4sf, movv16sf): Introduce insns that get split only after
reload.
* config/sh/shmedia.h: Fix Copyright dates.
* config/sh/ushmedia.h: Likewise. Move loop counter
declarations into conditionals that uses them.
(sh_media_FVADD_S, sh_media_FVSUB_S): Fix off-by-one error in
loop boundary.
* config/sh/sshmedia.h: Fix Copyright dates.
(sh_media_PUTCFG): Fix constraints.
2001-05-12 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (TARGET_PTRMEMFUNC_VBIT_LOCATION): Define to
ptrmemfunc_vbit_in_delta for SH5.
2001-05-08 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (TARGET_SWITCHES): Document -m5-*.
* invoke.texi: Likewise.
2001-04-14 Alexandre Oliva <aoliva@redhat.com>
* config/sh/lib1funcs.asm (GCC_push_shmedia_regs,
GCC_push_shmedia_regs_nofpu, GCC_pop_shmedia_regs,
GCC_pop_shmedia_regs_nofpu): New global symbols.
* config/sh/t-sh64 (LIB1ASMFUNCS): Add them.
* config/sh/sh.h (SHMEDIA_REGS_STACK_ADJUST): New macro.
* config/sh/sh.c (calc_live_regs): Account for PR's saving in
compact function with nonlocal labels.
(sh_expand_prologue) [SHcompact]: Push SHmedia regs if needed.
(sh_expand_epilogue) [SHcompact]: Pop them when appropriate.
(initial_elimination_offset): Account for their stack space.
* config/sh/sh.md (shmedia_save_restore_regs_compact): New insn.
* config/sh/sh.md (movsi_media, movsi_media_nofpu, movqi_media,
movhi_media, movdi_media, movdi_media_nofpu, movdf_media,
movdf_media_nofpu, movsf_media, movsf_media_nofpu): Require at
least one of the operands to be a register.
(movv2sf): Likewise. Renamed to movv2sf_i.
(movdi, movdf, movv2sf, movv4sf, movv16sf, movsf):
prepare_move_operands() before emitting SHmedia insns.
2001-04-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/crti.asm (init, fini) [__SH5__ && ! __SHMEDIA__]:
Don't save nor initialize r12. Don't mis-align the stack.
Pad the code with a nop.
* config/sh/crti.asm: Don't restore r12. Don't mis-align the
stack.
2001-03-13 Alexandre Oliva <aoliva@redhat.com>
* gcc/longlong.h (__umulsidi3, count_leading_zeros)
[__SHMEDIA__]: Implement.
2001-03-11 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md: Set latency of `pt' closer to reality.
(movsi_media, movsi_media_nofpu, movdi_media, movdi_media_nofpu,
movdf_media, movdf_media_nofpu, movsf_media, movsf_media_nofpu):
Set move, load and store type attributes.
* config/sh/sh.c (sh_loop_align) [TARGET_SH5]: Set to 3.
* config/sh/sh.h (OVERRIDE_OPTIONS) [TARGET_SH5]: Disable
profiling.
* config/sh/sh.h (PROMOTE_MODE): Sign-extend SImode to DImode.
* config/sh/sh-protos.h (sh_media_register_for_return): Declare.
* config/sh/sh.c (sh_media_register_for_return): New function.
(sh_expand_prologue) [TARGET_SHMEDIA]: Copy r18 to an available
branch-target register.
(sh_expand_epilogue) [TARGET_SHMEDIA]: Explicitly USE it.
* config/sh/sh.md (return_media_i): Use any call-clobbered
branch-target register.
(return_media): If r18 wasn't copied in the prologue, copy it
here.
* config/sh/sh.h (CONDITIONAL_REGISTER_USAGE) [TARGET_SHMEDIA]:
Clear class FP0_REGS.
* config/sh/sh64.h (LINK_SPEC): Removed incorrect default copied
from elf.h.
2001-03-08 DJ Delorie <dj@redhat.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Disable relaxing for SHMEDIA.
2001-02-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (sibcall_compact): Set fp_mode to single.
2001-02-07 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (INT_ASM_OP) [SHMEDIA64]: Use `.quad'.
2001-02-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (INIT_CUMULATIVE_ARGS): Compute size of BLKmode
return value correctly for call_cookie.
2001-02-01 Alexandre Oliva <aoliva@redhat.com>
* config/sh/crt1.asm (start): Modified so as to call
___setup_argv_and_call_main.
2001-01-26 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Don't count stack_regs in
SHmedia mode.
2001-01-20 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (STRIP_DATALABEL_ENCODING): New macro.
(STRIP_NAME_ENCODING): Use it.
(ASM_OUTPUT_LABELREF): Likewise. Don't call assemble_name().
2001-01-19 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (sgeu) [! SHMEDIA]: Fix invocation of
prepare_scc_operands().
* config/sh/sh.h (SH_DATALABEL_ENCODING): Change to "#"...
(DATALABEL_SYMNAME_P): ... so that we don't need memcmp here.
2001-01-17 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (STRIP_NAME_ENCODING): Strip leading `*'.
2001-01-13 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (shcompact_incoming_args): Use R0_REG.
* config/sh/sh.md (R7_REG, R8_REG, R9_REG): Define as constants,
used in shcompact_incoming_args.
* config/sh/sh.c (sh_expand_epilogue): Fix thinko in previous
change.
* config/sh/crt1.asm (start) [SH5]: Switch to single-precision
mode.
* config/sh/lib1funcs.asm (sdivsi3_i4, udivsi3_i4, set_fpscr):
Adjust accordingly.
* config/sh/sh.c (sh_expand_prologue, sh_expand_epilogue):
Simplify. Adjust. Add sanity check.
* config/sh/sh.h (TARGET_SWITCHES) [5-compact]: Set
FPU_SINGLE_BIT.
* config/sh/sh.md (udivsi3_i4_single, divsi3_i4_single): Match
TARGET_SHCOMPACT.
(udivsi3, divsi3): Use them.
(force_mode_for_call): New insn.
(call, call_value, sibcall_value): Emit it before SHcompact
calls.
2001-01-11 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (call, call_value, sibcall): Make sure the
call cookie is non-NULL before taking its value.
2001-01-10 Alexandre Oliva <aoliva@redhat.com>
* config.gcc (sh64): Set target_requires_64bit_host_wide_int.
2001-01-09 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (shcompact_incoming_args): Set argument memory
block.
* config/sh/sh.h (STATIC_CHAIN_REGNUM) [SH5]: Use r1.
* config/sh/sh.c (sh_expand_prologue) [SH5]: Use r0 as
temporary for stack adjusts. Use MACL and MACH to pass
arguments to shcompact_incoming_args.
* config/sh/sh.md (shcompact_incoming_args): Adjust. Don't
clobber r1.
* config/sh/lib1funcs.asm (shcompact_incoming_args): Likewise.
(nested_trampoline): Load static chain address into r1.
* config/sh/sh.md (movdi_media splits): Fix sign-extension.
2001-01-07 Alexandre Oliva <aoliva@redhat.com
* config/sh/sh.c (fpul_operand) [SHMEDIA]: Just call
fp_arith_reg_operand().
2001-01-06 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (casesi): Sign-extend the first two operands,
and use signed compares for them.
* config/sh/sh.c (dump_table): Don't emit 8-byte constants after
4-byte ones. Instead, inter-leave them, maintaining the 8-byte
ones properly aligned.
(find_barrier): Account for extra alignment needed for 8-byte wide
constants.
(machine_dependent_reorg): Require a label for the second 4-byte
constant after an 8-byte one.
* config/sh/lib1funcs.asm (sdivsi3): Fix typo in yesterday's
change.
2001-01-05 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (machine_dependent_reorg) [SHCOMPACT]: Reset
last_float when switching float modes.
* config/sh/sh.md (movdf) [SH5]: Don't use stack-pointer
auto-increment for general-purpose registers.
* config/sh/lib1funcs.asm (sdivsi3) [SHMEDIA]: Sign-extend the
result.
* config/sh/sh.c (sh_expand_prologue) [SH5]: Use r1 as temporary
for stack adjust.
* config/sh/sh.c (sh_builtin_saveregs): Support using all
registers for varargs.
2001-01-01 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Simplify.
* config/sh/sh.h (CALL_COOKIE_STACKSEQ,
CALL_COOKIE_STACKSEQ_SHIFT, CALL_COOKIE_STACKSEQ_GET): New macros.
(CALL_COOKIE_INT_REG_SHIFT): Adjust.
(FUNCTION_ARG_ADVANCE): Use SHCOMPACT_FORCE_ON_STACK. Adjust
call_cookie accordingly.
(FUNCTION_ARG): Test SHCOMPACT_FORCE_ON_STACK.
(SHCOMPACT_BYREF): Likewise.
(SHCOMPACT_FORCE_ON_STACK): New macro.
* config/sh/sh.c (sh_expand_prologue): Use new call_cookie format.
(sh_builtin_saveregs): Likewise.
* config/sh/lib1funcs.asm (shcompact_call_trampoline,
shcompact_incoming_args): Use new shift values. Support
sequences of consecutive and non-consecutive pushes/pops.
* config/sh/sh.md (return): Don't explicitly use PR_REG.
2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com>
* config/sh/sh.h (TEXT_SECTION): Define.
* config/sh/elf.h (ASM_FILE_START): Output TEXT_SECTION_ASM_OP.
2001-01-05 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (INIT_CUMULATIVE_LIBCALL_ARGS): New macro.
* config/sh/sh.h (BASE_RETURN_VALUE_REG): Use FP regs for
return values on FPU-enabled SHmedia.
(FUNCTION_VALUE_REGNO_P): Mark FIRST_FP_RET_REG as used on
FPU-enabled SHmedia.
(INIT_CUMULATIVE_ARGS): Set up return trampoline only if
value is returned in a non-FP reg and is not returned by
reference.
* config/sh/sh.md (shcompact_return_tramp_i): Change type to
jump_ind.
2000-01-04 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (SH_MIN_ALIGN_FOR_CALLEE_COPY): New.
(FUNCTION_ARG_CALLEE_COPIES): Require argument to be
quad-aligned to be passed by callee-copy reference.
2001-01-03 Alexandre Oliva <aoliva@redhat.com>
* config/sh/elf.h (MAX_WCHAR_TYPE_SIZE): Define.
* config/sh/sh64.h (MAX_WCHAR_TYPE_SIZE): Undefine.
2001-01-02 Alexandre Oliva <aoliva@redhat.com>
* config/sh/lib1funcs.asm (shcompact_call_trampoline): Fix error in
copying low-numbered FP regs to r7 and r8.
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Don't request copying of
FP regs to general-purpose regs only if the copy was passed on the
stack.
* config/sh/lib1funcs.asm (shcompact_call_trampoline): Fix typo in
copying FP reg to r9.
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Use trampoline to
copy FP regs to general-purpose regs only in outgoing calls.
* config/sh/sh.md (movdf_media, movsf_media): Revert incorrect
change from 2000-10-30. Adjust for 64-bit (or 32-bit)
HOST_WIDE_INT.
* config/sh/sh.h (struct sh_args): Document all fields.
(FUNCTION_OK_FOR_SIBCALL): Functions that receive arguments
passed partially on the stack should not consider making
sibcalls.
* config/sh/sh.h (FUNCTION_ARG_ADVANCE): Add byref regs to
stack_regs only for incoming calls. When passing FP args,
make sure there are FP regs available before modifying
call_cookie.
(SHCOMPACT_BYREF): Pass double args in general-purpose
registers by reference.
2000-12-30 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (FUNCTION_OK_FOR_SIBCALL) [SHCOMPACT]: Don't
attempt to generate sibcalls if the caller got any arguments
by reference.
* config/sh/lib1funcs.asm (set_fpscr) [SH5]: Default to double.
* config/sh/sh.c (dump_table) [SHCOMPACT]: Align DImode and DFmode
to 8-byte boundaries.
* config/sh/sh.md (shcompact_preserve_incoming_args): New insn.
* config/sh/sh.h (CALL_COOKIE_INT_REG_GET): New macro.
* config/sh/sh.c (sh_expand_prologue): Preserve args that will be
stored in the stack.
* config/sh/lib1funcs.asm (ct_main_table, ia_main_table): Arrange
for the offsets to have the ISA bit set.
(shcompact_call_trampoline): Document. Swap r0 and r1, to match
invocation. Use beq instead of bgt to mark end of sequence of
loads.
(shcompact_incoming_args): Fix store of r2. Use beq instead of
bgt to mark end of sequence of stores.
* config/sh/sh.c (arith_operand): Don't check whether
CONST_OK_FOR_J for now.
* config/sh/sh.md (movdf_media, movsf_media): Use HOST_WIDE_INT
instead of long for conversion.
2000-12-29 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.c (print_operand_address): Convert INTVAL to int
before passing it to fprintf.
2000-12-28 Alexandre Oliva <aoliva@redhat.com>
* config/sh/crt1.asm (start): Reset SR.FD, to enable the FP unit.
Call set_fpscr before reading/writing SR.
* config/sh/crt1.asm (start): Set SR.SZ and SR.PR, but not SR.FR.
Call set_fpscr.
* config/sh/lib1funcs.asm: Add `.align 2' directives before
SHmedia code.
(FMOVD_WORKS): Define on SH5 with FPU.
(set_fpscr): Define on SH5. Remove separate _fpscr_values
setting.
* config/sh/t-sh64 (LIB1ASMFUNCS): Add _set_fpscr instead of
_fpscr_values.
2000-12-28 Hans-Peter Nilsson <hpn@cygnus.com>
* config/sh/lib1funcs.asm (ct_main_table): Align contents to even
address.
(ia_main_table): Ditto.
2000-12-27 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.h (MAX_WCHAR_TYPE_SIZE): Don't define.
* config/sh/sh64.h (WCHAR_TYPE, WCHAR_TYPE_SIZE): Reinstate
the definitions from sh.h.
* config/sh/sh.h (PTRDIFF_TYPE): Define as conditional on
TARGET_SH5.
(SUBTARGET_CPP_SPEC): Arrange for __PTRDIFF_TYPE__ to be defined.
* config/sh/elf.h (PTRDIFF_TYPE): Likewise.
* config/sh/sh64.h (SUBTARGET_CPP_SPEC): Likewise.
2000-12-26 Alexandre Oliva <aoliva@redhat.com>
* config/sh/sh.md (movdi_media split): Don't add REG_LABEL notes.
Increment LABEL_NUSES.
From-SVN: r49630
2002-02-09 03:08:08 +00:00
|
|
|
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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#ifdef L_div_table
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2016-04-29 14:10:26 +00:00
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#if defined (__SH2A__) || defined (__SH3__) || defined (__SH3E__) || defined (__SH4__) || defined (__SH4_SINGLE__) || defined (__SH4_SINGLE_ONLY__) || defined (__SH4_NOFPU__)
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2013-03-06 00:41:25 +00:00
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/* This code uses shld, thus is not suitable for SH1 / SH2. */
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2006-03-23 21:39:32 +00:00
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/* Signed / unsigned division without use of FPU, optimized for SH4.
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Uses a lookup table for divisors in the range -128 .. +128, and
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div1 with case distinction for larger divisors in three more ranges.
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The code is lumped together with the table to allow the use of mova. */
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#ifdef __LITTLE_ENDIAN__
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#define L_LSB 0
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#define L_LSWMSB 1
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#define L_MSWLSB 2
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#else
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#define L_LSB 3
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#define L_LSWMSB 2
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#define L_MSWLSB 1
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#endif
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.balign 4
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.global GLOBAL(udivsi3_i4i)
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FUNC(GLOBAL(udivsi3_i4i))
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GLOBAL(udivsi3_i4i):
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mov.w LOCAL(c128_w), r1
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div0u
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mov r4,r0
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shlr8 r0
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cmp/hi r1,r5
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extu.w r5,r1
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bf LOCAL(udiv_le128)
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cmp/eq r5,r1
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bf LOCAL(udiv_ge64k)
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shlr r0
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mov r5,r1
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shll16 r5
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mov.l r4,@-r15
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div1 r5,r0
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mov.l r1,@-r15
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div1 r5,r0
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div1 r5,r0
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bra LOCAL(udiv_25)
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div1 r5,r0
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LOCAL(div_le128):
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mova LOCAL(div_table_ix),r0
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bra LOCAL(div_le128_2)
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mov.b @(r0,r5),r1
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LOCAL(udiv_le128):
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mov.l r4,@-r15
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mova LOCAL(div_table_ix),r0
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mov.b @(r0,r5),r1
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mov.l r5,@-r15
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LOCAL(div_le128_2):
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mova LOCAL(div_table_inv),r0
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mov.l @(r0,r1),r1
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mov r5,r0
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tst #0xfe,r0
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mova LOCAL(div_table_clz),r0
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dmulu.l r1,r4
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mov.b @(r0,r5),r1
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bt/s LOCAL(div_by_1)
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mov r4,r0
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mov.l @r15+,r5
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sts mach,r0
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/* clrt */
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addc r4,r0
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mov.l @r15+,r4
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rotcr r0
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rts
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shld r1,r0
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LOCAL(div_by_1_neg):
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neg r4,r0
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LOCAL(div_by_1):
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mov.l @r15+,r5
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rts
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mov.l @r15+,r4
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LOCAL(div_ge64k):
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bt/s LOCAL(div_r8)
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div0u
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shll8 r5
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bra LOCAL(div_ge64k_2)
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div1 r5,r0
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LOCAL(udiv_ge64k):
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cmp/hi r0,r5
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mov r5,r1
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bt LOCAL(udiv_r8)
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shll8 r5
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mov.l r4,@-r15
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div1 r5,r0
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mov.l r1,@-r15
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LOCAL(div_ge64k_2):
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div1 r5,r0
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mov.l LOCAL(zero_l),r1
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.rept 4
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div1 r5,r0
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.endr
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mov.l r1,@-r15
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div1 r5,r0
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mov.w LOCAL(m256_w),r1
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div1 r5,r0
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mov.b r0,@(L_LSWMSB,r15)
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xor r4,r0
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and r1,r0
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bra LOCAL(div_ge64k_end)
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xor r4,r0
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LOCAL(div_r8):
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shll16 r4
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bra LOCAL(div_r8_2)
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shll8 r4
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LOCAL(udiv_r8):
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mov.l r4,@-r15
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shll16 r4
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clrt
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shll8 r4
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mov.l r5,@-r15
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LOCAL(div_r8_2):
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rotcl r4
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mov r0,r1
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div1 r5,r1
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mov r4,r0
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rotcl r0
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mov r5,r4
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div1 r5,r1
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.rept 5
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rotcl r0; div1 r5,r1
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.endr
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rotcl r0
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mov.l @r15+,r5
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div1 r4,r1
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mov.l @r15+,r4
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rts
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rotcl r0
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ENDFUNC(GLOBAL(udivsi3_i4i))
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.global GLOBAL(sdivsi3_i4i)
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FUNC(GLOBAL(sdivsi3_i4i))
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/* This is link-compatible with a GLOBAL(sdivsi3) call,
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but we effectively clobber only r1. */
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GLOBAL(sdivsi3_i4i):
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mov.l r4,@-r15
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cmp/pz r5
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mov.w LOCAL(c128_w), r1
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bt/s LOCAL(pos_divisor)
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cmp/pz r4
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mov.l r5,@-r15
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neg r5,r5
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bt/s LOCAL(neg_result)
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cmp/hi r1,r5
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neg r4,r4
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LOCAL(pos_result):
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extu.w r5,r0
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bf LOCAL(div_le128)
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cmp/eq r5,r0
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mov r4,r0
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shlr8 r0
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bf/s LOCAL(div_ge64k)
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cmp/hi r0,r5
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div0u
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shll16 r5
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div1 r5,r0
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div1 r5,r0
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div1 r5,r0
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LOCAL(udiv_25):
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mov.l LOCAL(zero_l),r1
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div1 r5,r0
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div1 r5,r0
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mov.l r1,@-r15
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.rept 3
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div1 r5,r0
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.endr
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mov.b r0,@(L_MSWLSB,r15)
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xtrct r4,r0
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swap.w r0,r0
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.rept 8
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div1 r5,r0
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.endr
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mov.b r0,@(L_LSWMSB,r15)
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LOCAL(div_ge64k_end):
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.rept 8
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div1 r5,r0
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.endr
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mov.l @r15+,r4 ! zero-extension and swap using LS unit.
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extu.b r0,r0
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mov.l @r15+,r5
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or r4,r0
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mov.l @r15+,r4
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rts
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rotcl r0
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LOCAL(div_le128_neg):
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tst #0xfe,r0
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mova LOCAL(div_table_ix),r0
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mov.b @(r0,r5),r1
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mova LOCAL(div_table_inv),r0
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bt/s LOCAL(div_by_1_neg)
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mov.l @(r0,r1),r1
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mova LOCAL(div_table_clz),r0
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dmulu.l r1,r4
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mov.b @(r0,r5),r1
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mov.l @r15+,r5
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sts mach,r0
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/* clrt */
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addc r4,r0
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mov.l @r15+,r4
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rotcr r0
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shld r1,r0
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rts
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neg r0,r0
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LOCAL(pos_divisor):
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mov.l r5,@-r15
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bt/s LOCAL(pos_result)
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cmp/hi r1,r5
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neg r4,r4
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LOCAL(neg_result):
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extu.w r5,r0
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bf LOCAL(div_le128_neg)
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cmp/eq r5,r0
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mov r4,r0
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shlr8 r0
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bf/s LOCAL(div_ge64k_neg)
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cmp/hi r0,r5
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div0u
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mov.l LOCAL(zero_l),r1
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shll16 r5
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div1 r5,r0
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mov.l r1,@-r15
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.rept 7
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div1 r5,r0
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.endr
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mov.b r0,@(L_MSWLSB,r15)
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xtrct r4,r0
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swap.w r0,r0
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.rept 8
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div1 r5,r0
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.endr
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mov.b r0,@(L_LSWMSB,r15)
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LOCAL(div_ge64k_neg_end):
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.rept 8
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div1 r5,r0
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.endr
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mov.l @r15+,r4 ! zero-extension and swap using LS unit.
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extu.b r0,r1
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mov.l @r15+,r5
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or r4,r1
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LOCAL(div_r8_neg_end):
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mov.l @r15+,r4
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rotcl r1
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rts
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neg r1,r0
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|
|
|
|
|
LOCAL(div_ge64k_neg):
|
|
|
|
|
bt/s LOCAL(div_r8_neg)
|
|
|
|
|
div0u
|
|
|
|
|
shll8 r5
|
|
|
|
|
mov.l LOCAL(zero_l),r1
|
|
|
|
|
.rept 6
|
|
|
|
|
div1 r5,r0
|
|
|
|
|
.endr
|
|
|
|
|
mov.l r1,@-r15
|
|
|
|
|
div1 r5,r0
|
|
|
|
|
mov.w LOCAL(m256_w),r1
|
|
|
|
|
div1 r5,r0
|
|
|
|
|
mov.b r0,@(L_LSWMSB,r15)
|
|
|
|
|
xor r4,r0
|
|
|
|
|
and r1,r0
|
|
|
|
|
bra LOCAL(div_ge64k_neg_end)
|
|
|
|
|
xor r4,r0
|
|
|
|
|
|
|
|
|
|
LOCAL(c128_w):
|
|
|
|
|
.word 128
|
|
|
|
|
|
|
|
|
|
LOCAL(div_r8_neg):
|
|
|
|
|
clrt
|
|
|
|
|
shll16 r4
|
|
|
|
|
mov r4,r1
|
|
|
|
|
shll8 r1
|
|
|
|
|
mov r5,r4
|
|
|
|
|
.rept 7
|
|
|
|
|
rotcl r1; div1 r5,r0
|
|
|
|
|
.endr
|
|
|
|
|
mov.l @r15+,r5
|
|
|
|
|
rotcl r1
|
|
|
|
|
bra LOCAL(div_r8_neg_end)
|
|
|
|
|
div1 r4,r0
|
|
|
|
|
|
|
|
|
|
LOCAL(m256_w):
|
|
|
|
|
.word 0xff00
|
|
|
|
|
/* This table has been generated by divtab-sh4.c. */
|
|
|
|
|
.balign 4
|
|
|
|
|
LOCAL(div_table_clz):
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte 1
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte -1
|
|
|
|
|
.byte -1
|
|
|
|
|
.byte -2
|
|
|
|
|
.byte -2
|
|
|
|
|
.byte -2
|
|
|
|
|
.byte -2
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -3
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -5
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -6
|
|
|
|
|
/* Lookup table translating positive divisor to index into table of
|
|
|
|
|
normalized inverse. N.B. the '0' entry is also the last entry of the
|
|
|
|
|
previous table, and causes an unaligned access for division by zero. */
|
|
|
|
|
LOCAL(div_table_ix):
|
|
|
|
|
.byte -6
|
|
|
|
|
.byte -128
|
|
|
|
|
.byte -128
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte -128
|
|
|
|
|
.byte -64
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte 64
|
|
|
|
|
.byte -128
|
|
|
|
|
.byte -96
|
|
|
|
|
.byte -64
|
|
|
|
|
.byte -32
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte 32
|
|
|
|
|
.byte 64
|
|
|
|
|
.byte 96
|
|
|
|
|
.byte -128
|
|
|
|
|
.byte -112
|
|
|
|
|
.byte -96
|
|
|
|
|
.byte -80
|
|
|
|
|
.byte -64
|
|
|
|
|
.byte -48
|
|
|
|
|
.byte -32
|
|
|
|
|
.byte -16
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte 16
|
|
|
|
|
.byte 32
|
|
|
|
|
.byte 48
|
|
|
|
|
.byte 64
|
|
|
|
|
.byte 80
|
|
|
|
|
.byte 96
|
|
|
|
|
.byte 112
|
|
|
|
|
.byte -128
|
|
|
|
|
.byte -120
|
|
|
|
|
.byte -112
|
|
|
|
|
.byte -104
|
|
|
|
|
.byte -96
|
|
|
|
|
.byte -88
|
|
|
|
|
.byte -80
|
|
|
|
|
.byte -72
|
|
|
|
|
.byte -64
|
|
|
|
|
.byte -56
|
|
|
|
|
.byte -48
|
|
|
|
|
.byte -40
|
|
|
|
|
.byte -32
|
|
|
|
|
.byte -24
|
|
|
|
|
.byte -16
|
|
|
|
|
.byte -8
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte 8
|
|
|
|
|
.byte 16
|
|
|
|
|
.byte 24
|
|
|
|
|
.byte 32
|
|
|
|
|
.byte 40
|
|
|
|
|
.byte 48
|
|
|
|
|
.byte 56
|
|
|
|
|
.byte 64
|
|
|
|
|
.byte 72
|
|
|
|
|
.byte 80
|
|
|
|
|
.byte 88
|
|
|
|
|
.byte 96
|
|
|
|
|
.byte 104
|
|
|
|
|
.byte 112
|
|
|
|
|
.byte 120
|
|
|
|
|
.byte -128
|
|
|
|
|
.byte -124
|
|
|
|
|
.byte -120
|
|
|
|
|
.byte -116
|
|
|
|
|
.byte -112
|
|
|
|
|
.byte -108
|
|
|
|
|
.byte -104
|
|
|
|
|
.byte -100
|
|
|
|
|
.byte -96
|
|
|
|
|
.byte -92
|
|
|
|
|
.byte -88
|
|
|
|
|
.byte -84
|
|
|
|
|
.byte -80
|
|
|
|
|
.byte -76
|
|
|
|
|
.byte -72
|
|
|
|
|
.byte -68
|
|
|
|
|
.byte -64
|
|
|
|
|
.byte -60
|
|
|
|
|
.byte -56
|
|
|
|
|
.byte -52
|
|
|
|
|
.byte -48
|
|
|
|
|
.byte -44
|
|
|
|
|
.byte -40
|
|
|
|
|
.byte -36
|
|
|
|
|
.byte -32
|
|
|
|
|
.byte -28
|
|
|
|
|
.byte -24
|
|
|
|
|
.byte -20
|
|
|
|
|
.byte -16
|
|
|
|
|
.byte -12
|
|
|
|
|
.byte -8
|
|
|
|
|
.byte -4
|
|
|
|
|
.byte 0
|
|
|
|
|
.byte 4
|
|
|
|
|
.byte 8
|
|
|
|
|
.byte 12
|
|
|
|
|
.byte 16
|
|
|
|
|
.byte 20
|
|
|
|
|
.byte 24
|
|
|
|
|
.byte 28
|
|
|
|
|
.byte 32
|
|
|
|
|
.byte 36
|
|
|
|
|
.byte 40
|
|
|
|
|
.byte 44
|
|
|
|
|
.byte 48
|
|
|
|
|
.byte 52
|
|
|
|
|
.byte 56
|
|
|
|
|
.byte 60
|
|
|
|
|
.byte 64
|
|
|
|
|
.byte 68
|
|
|
|
|
.byte 72
|
|
|
|
|
.byte 76
|
|
|
|
|
.byte 80
|
|
|
|
|
.byte 84
|
|
|
|
|
.byte 88
|
|
|
|
|
.byte 92
|
|
|
|
|
.byte 96
|
|
|
|
|
.byte 100
|
|
|
|
|
.byte 104
|
|
|
|
|
.byte 108
|
|
|
|
|
.byte 112
|
|
|
|
|
.byte 116
|
|
|
|
|
.byte 120
|
|
|
|
|
.byte 124
|
|
|
|
|
.byte -128
|
|
|
|
|
/* 1/64 .. 1/127, normalized. There is an implicit leading 1 in bit 32. */
|
|
|
|
|
.balign 4
|
|
|
|
|
LOCAL(zero_l):
|
|
|
|
|
.long 0x0
|
|
|
|
|
.long 0xF81F81F9
|
|
|
|
|
.long 0xF07C1F08
|
|
|
|
|
.long 0xE9131AC0
|
|
|
|
|
.long 0xE1E1E1E2
|
|
|
|
|
.long 0xDAE6076C
|
|
|
|
|
.long 0xD41D41D5
|
|
|
|
|
.long 0xCD856891
|
|
|
|
|
.long 0xC71C71C8
|
|
|
|
|
.long 0xC0E07039
|
|
|
|
|
.long 0xBACF914D
|
|
|
|
|
.long 0xB4E81B4F
|
|
|
|
|
.long 0xAF286BCB
|
|
|
|
|
.long 0xA98EF607
|
|
|
|
|
.long 0xA41A41A5
|
|
|
|
|
.long 0x9EC8E952
|
|
|
|
|
.long 0x9999999A
|
|
|
|
|
.long 0x948B0FCE
|
|
|
|
|
.long 0x8F9C18FA
|
|
|
|
|
.long 0x8ACB90F7
|
|
|
|
|
.long 0x86186187
|
|
|
|
|
.long 0x81818182
|
|
|
|
|
.long 0x7D05F418
|
|
|
|
|
.long 0x78A4C818
|
|
|
|
|
.long 0x745D1746
|
|
|
|
|
.long 0x702E05C1
|
|
|
|
|
.long 0x6C16C16D
|
|
|
|
|
.long 0x68168169
|
|
|
|
|
.long 0x642C8591
|
|
|
|
|
.long 0x60581606
|
|
|
|
|
.long 0x5C9882BA
|
|
|
|
|
.long 0x58ED2309
|
|
|
|
|
LOCAL(div_table_inv):
|
|
|
|
|
.long 0x55555556
|
|
|
|
|
.long 0x51D07EAF
|
|
|
|
|
.long 0x4E5E0A73
|
|
|
|
|
.long 0x4AFD6A06
|
|
|
|
|
.long 0x47AE147B
|
|
|
|
|
.long 0x446F8657
|
|
|
|
|
.long 0x41414142
|
|
|
|
|
.long 0x3E22CBCF
|
|
|
|
|
.long 0x3B13B13C
|
|
|
|
|
.long 0x38138139
|
|
|
|
|
.long 0x3521CFB3
|
|
|
|
|
.long 0x323E34A3
|
|
|
|
|
.long 0x2F684BDB
|
|
|
|
|
.long 0x2C9FB4D9
|
|
|
|
|
.long 0x29E4129F
|
|
|
|
|
.long 0x27350B89
|
|
|
|
|
.long 0x24924925
|
|
|
|
|
.long 0x21FB7813
|
|
|
|
|
.long 0x1F7047DD
|
|
|
|
|
.long 0x1CF06ADB
|
|
|
|
|
.long 0x1A7B9612
|
|
|
|
|
.long 0x18118119
|
|
|
|
|
.long 0x15B1E5F8
|
|
|
|
|
.long 0x135C8114
|
|
|
|
|
.long 0x11111112
|
|
|
|
|
.long 0xECF56BF
|
|
|
|
|
.long 0xC9714FC
|
|
|
|
|
.long 0xA6810A7
|
|
|
|
|
.long 0x8421085
|
|
|
|
|
.long 0x624DD30
|
|
|
|
|
.long 0x4104105
|
|
|
|
|
.long 0x2040811
|
|
|
|
|
/* maximum error: 0.987342 scaled: 0.921875*/
|
|
|
|
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ENDFUNC(GLOBAL(sdivsi3_i4i))
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#endif /* SH3 / SH4 */
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re PR target/20695 (sh64-*-* port deos not handle 32 / 64 bit conversions properly)
gcc:
2005-05-09 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh.h (OVERRIDE_OPTIONS): Don't set flag_finite_math_only
if flag_signaling_nans is set.
For TARGET_SH2E, if flag_finite_math_only is not set, set IEEE_BIT.
* doc/invoke.texi (SH -mieee): Document relation to -ffinite-math-only.
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of sh-elf specific patches from sh-elf-4_1-branch:
2005-05-05 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.h (ASM_OUTPUT_REG_PUSH): Provide SHMEDIA version.
(ASM_OUTPUT_REG_POP): Likewise.
2005-05-05 J"orn Rennecke <joern.rennecke@st.com>
Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_builtin_saveregs): Use copy_to_mode_reg
and plus_constant.
2005-05-04 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/sh.c (sh_div_strategy): Initialize with
SH_DIV_STRATEGY_DEFAULT.
* config/sh/sh.c (SH_DIV_STR_FOR_SIZE): Define.
(SH_DIV_STRATEGY_DEFAULT): Likewise.
(OPTIMIZATION_OPTIONS): Set sh_div_str to SH_DIV_STR_FOR_SIZE
when optimized for size.
* config/sh/linux.h (SH_DIV_STRATEGY_DEFAULT): Redefine.
(SH_DIV_STR_FOR_SIZE): Likewise.
* config/sh/netbsd-elf.h (SH_DIV_STRATEGY_DEFAULT): Likewise.
(SH_DIV_STR_FOR_SIZE): Likewise.
2005-05-04 J"orn Rennecke <joern.rennecke@st.com>
* config/sh/sh-modes.def (PDImode): Add.
* config/sh/sh-protos.h (shmedia_prepare_call_address): Declare.
* config/sh/sh.c (print_operand): Handle IF_THEN_ELSE.
(target_reg_operand): Allow PDImode.
(sh_register_move_cost): If neither sh_gettrcost_str nor
TARGET_PT_FIXED is set, assume gettr costs 100.
(shmedia_prepare_call_address): New function.
(sh_gettrcost_str): Initialize to empty string.
(sh_divsi3_libfunc): New variable.
* config/sh/sh.h (PT_FIXED_BIT, TARGET_INVALID_SYMBOLS): Define.
(TARGET_SWITCH_SH5_32_ANY_EXTRA): Likewise.
(TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA): Likewise.
(TARGET_SWITCHES): Use TARGET_SWITCH_SH5_32_ANY_EXTRA and
TARGET_SWITCH_SH5_MEDIA_ANY_EXTRA.
(TARGET_OPTIONS): Add -mdivsi3_libfunc.
(OVERRIDE_OPTIONS): Set sh_divsi3_libfunc if it hasn't been set
by the user.
Also set flag_no_function_cse for (TARGET_SHMEDIA && !TARGET_PT_FIXED).
(HARD_REGNO_MODE_OK): Allow TARGET_REGS in PDImode.
(CONSTRAINT_LEN): Remove debug version.
(SECONDARY_INOUT_RELOAD_CLASS:) Break out of
(SECONDARY_OUTPUT_RELOAD_CLASS). Use EXTRA_CONSTRAINT_Csy for check
if a target register needs a secondary reload through GENERAL_REGS.
(SECONDARY_INPUT_RELOAD_CLASS): Use SECONDARY_INOUT_RELOAD_CLASS.
(sh_divsi3_libfunc): Declare.
(FUNCTION_PROFILER): Provide SHMEDIA version.
* config/sh/predicates.md: New file.
* config/sh/sh.md (predicates.md): Include.
(divsi_inv_call_combine, divsi3): Use sh_divsi3_libfunc.
(reload_insi): Fix predicates and constraints.
(ptabs): New expander.
(*extendsipdi_media, *truncdipdi_media): New insns.
(call, call_value, sibcall): Use shmedia_prepare_call_address.
* doc/invoke.texi (-multcost, -mdiv): Document new SH options.
(-mdivsi3_libfunc, -madjust-unroll, -mindexed-addressing): Likewise.
(-mgettrcost, -mpt-fixed, -minvalid-symbols): Likewise.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.c (print_operand): Remove sh_rep_vec extraction.
(sh_output_mi_thunk): Make i unsigned.
* sh.c (TARGET_ADJUST_UNROLL_MAX): Only redefine if already defined.
(sh_adjust_unroll_max): Only define if TARGET_ADJUST_UNROLL_MAX
is defined. Update label detection code and iteration lookup,
enable basic functionality, but without IV analysis.
2005-04-11 J"orn Rennecke <joern.rennecke@st.com>
* sh.h (OPTIMIZATION_OPTIONS): Don't make setting of
flag_branch_target_load_optimize dependent on TARGET_SHMEDIA.
Set flag_finite_math_only to 2.
If flag_finite_math_only set set to 2, set it to 1 iff
we use SH2E..SH4 arithmetic without full IEEE support.
2005-04-09 Kaz Kojima <kkojima@gcc.gnu.org>
* config/sh/lib1funcs.asm (ic_invalidate): Fix typos.
* config/sh/t-linux (LIB1ASMFUNCS_CACHE): Add _ic_invalidate_array.
2005-04-06 J"orn Rennecke <joern.rennecke@st.com>
Merge of SuperH / STM SH specific patches, including fix for
PR target/20695:
* config.gcc (sh*-superh-elf, sh*elf (newlib)): Use newlib.h
when building with libgloss.
(sh*elf): Implement --without-fp option.
(sh64-superh-linux*): Don't multilib.
(sh*-*-linux): Use sh3 as basic multilib.
* config/sh/crt1.asm (SHmedia start): Add code to enable the MMU,
and to set up vbr. Enable FPU before calling set_fpscr.
Load atexit address just before use. Use __SH_FPU_ANY__.
(SH3*/SH4* start): Add code to set up vbr. Use __SH_FPU_ANY__.
Set DN bit in fpscr.
* config/sh/elf.h (SUBTARGET_ASM_ISA_SPEC): Merge into:
config/sh/sh.h (SH_ASM_SPEC, SUBTARGET_ASM_ISA_SPEC): Here.
* config/sh/lib1funcs.asm (HIDDEN_FUNC, HIDDEN_ALIAS): Define.
(FMOVD_WORKS): Don't define for __SH5__.
(ashiftrt_r4_0, ashiftrt_r4_1, ashiftrt_r4_2, ashiftrt_r4_3): Hide.
(ashiftrt_r4_4, ashiftrt_r4_5, ashiftrt_r4_6, ashiftrt_r4_7): Hide.
(ashiftrt_r4_8, ashiftrt_r4_9, ashiftrt_r4_10, ashiftrt_r4_11): Hide.
(ashiftrt_r4_12, ashiftrt_r4_13, ashiftrt_r4_14, ashiftrt_r4_15): Hide.
(ashiftrt_r4_16, ashiftrt_r4_17, ashiftrt_r4_18, ashiftrt_r4_19): Hide.
(ashiftrt_r4_20, ashiftrt_r4_21, ashiftrt_r4_22, ashiftrt_r4_23): Hide.
(ashiftrt_r4_24, ashiftrt_r4_25, ashiftrt_r4_26, ashiftrt_r4_27): Hide.
(ashiftrt_r4_28, ashiftrt_r4_29, ashiftrt_r4_30, ashiftrt_r4_31): Hide.
(ashiftrt_r4_32, ashrsi3, ashlsi3, lshrsi3, movmem, movstr): Hide.
(movstrSI64, movmemSI64, movstrSI60, movmemSI60): Hide.
(movstrSI56, movmemSI56, movstrSI52, movmemSI52): Hide.
(movstrSI48, movmemSI48, movstrSI44, movmemSI44): Hide.
(movstrSI40, movmemSI40, movstrSI36, movmemSI36): Hide.
(movstrSI32, movmemSI32, movstrSI28, movmemSI28): Hide.
(movstrSI24, movmemSI24, movstrSI20, movmemSI20): Hide.
(movstrSI16,movmemSI16, movstrSI12,movmemSI12): Hide.
(movstrSI8,movmemSI8, movstrSI4,movmemSI4): Hide.
(movmemSI0, movstrSI0): Remove.
(movmemSI4): Schedule last store into rts delay slot.
(movmem): Shorten code. Provide ENDFUNC.
(movmem_i4_even, movmem_i4_odd, movmemSI12_i4, mulsi3): Hide.
(mulsi3): Provide ENDFUNC.
(sdivsi3_i4, sdivsi3_i4, udivsi3_i4, udivsi3, set_fpscr): Hide.
(SH5 sdivsi3): Reimplement, using:
(div_table): New, linear approximation table lookup for division seed.
(sdivsi3_2): New SH5 entry point.
(divdi3): Use hidden alias for udivdi3.
(moddi3): Use hidden alias for umoddi3.
(init_trampoline): Hide. Provide exact ENDFUNC.
(ic_invalidate): Hide. Re-implement SH4 version, using
(ic_invalidate_array): New global.
(GCC_shcompact_return_trampoline, GCC_nested_trampoline): Hide.
(GCC_push_shmedia_regs_nofpu): Only provide for __SH4_NOFPU__.
(GCC_pop_shmedia_regs_nofpu): Likewise.
* config/sh/libgcc-excl.ver (__mulsi3): Add.
* config/sh/linux.h (TARGET_DEFAULT): Include TARGET_OPT_DEFAULT.
* config/sh/sh-protos.h (sh_function_kind): New enum.
(sh_gen_truncate, replace_n_hard_rtx): Declare.
(function_symbol): Update declaration.
(shmedia_cleanup_truncate, sh_contains_memref_p): Declare.
* sh.c (cfgloop.h): Include.
(TARGET_ADJUST_UNROLL_MAX): Redefine.
(print_operand): Add '>' and 'U' support. Handle TRUNCATE and
SIGN_EXTEND.
(function_sybol): Add arguments for target and kind of symbol.
If not an ordinary function symbol, make sure the string becomes
unique. For PIC, load appropriately depending on kind of symbol.
Changed all callers.
(prepare_move_operands): Dont copy R0 to a pseudo for SHmedia.
(multcosts): Check sh_multcost_str. If not set, return 2 for
SHMEDIA TARGET_SMALLCODE.
(sh_rtx_costs): Lower some costs when outer_code is SET. Add code
for CONST_VECTOR, MINUS and PARALLEL.
(gen_shifty_op): Don't emit nop.
(expand_ashiftrt): While expanding to rtl, do shift by 31 using a
register set to zero.
(gen_datalabel_ref): Make sure that the string is shared.
(MAX_POOL_SIZE): Define as 372.
(find_barrier): Remove spurious adjustment.
(sh_media_register_for_return): Return -1 for interrupt handlers.
(sh_pch_valid_p): Use a copy of TARGET_OPTIONS.
(general_movsrc_operand): Accept vector that match sh_rep_vec.
(general_movdst_operand): For SHmedia, recject paradoxical DImode
subregs before high_life / reload.
(arith_reg_operand): Allow no-op sign extensions.
(logical_reg_operand, fp_arith_reg_dest, xor_operand): New functions.
(cmp_operand, shift_operator, logical_operator): Likewise.
(minuend_operand, ua_address_operand, cache_address_operand): Likewise.
(ua_offset, shift_count_reg_operand, shift_count_operand): Likewise.
(sh_adjust_unroll_max, replace_n_hard_rtx, sh_gen_truncate): Likewise.
(shmedia_cleanup_truncate, sh_contains_memref_p_1): Likewise.
(sh_contains_memref_p): Likewise.
(shmedia_6bit_operand): Remove.
(arith_operand): Allow some TRUNCATEs.
(logical_operand): Disallow subregs <= SImode of >= DImode.
(greater_comparison_operator): Fix mode comparison.
(less_comparison_operator): Likewise.
(target_reg_operand, target_operand): Compare modes with Pmode.
(sh_adjust_cost): Consider the dependency between a target register
load and its use in a subsequent block.
Implement mac_media latency exception.
Before reload, anticipate floating point latencies to be at least four.
Give preference to the ptabs feeding a casesi_jump_media.
Handle UNSPEC in a CALL address.
(sh_optimize_target_register_callee_saved): Improve handling of
borderline cases.
(sh_function_ok_for_sibcall): Allow for non-pic, and also when we
will use the symbol with @GOTOFF addressing.
(SH_BLTIN_UDI): Remove.
(SH_BLTIN_LDUA_L64, SH_BLTIN_LDUA_Q64, SH_BLTIN_STUA_L64): New.
(SH_BLTIN_STUA_Q64): Likewise.
(signature_args, SH_BLTIN_NUM_SHARED_SIGNATURES): Update.
(SH_BLTIN_2, SH_BLTIN_SU, SH_BLTIN_3, SH_BLTIN_SUS): Renumber.
(SH_BLTIN_PSSV, SH_BLTIN_XXUU, SH_BLTIN_UUUU, SH_BLTIN_PV): Likewise.
(bdesc): Add entries for alloco, mac_media, sqrtdf2, sqrtsf2, fsrra_s,
{ld,st}{hi,lo}.[lq] and prefetch.
Change mextr entries to use SH_BLTIN_V8QI3.
(sh_media_init_builtins): Implement specific TARGET_SHMEDIA32 /
TARGET_SHMEDIA64 checks for pointer arguments.
(sh_expand_builtin): For pointer types, use ptr_mode / ptr_type_mode.
(sh_register_move_cost): Check sh_gettrcost_str.
(cmpsi_operand): T_REG is only allowed for TARGET_SH1.
(sh_output_mi_thunk): Make static. Check that needed registers are
actually available. Make sure that the sibcall won't go via the PLT.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): New variables.
(cut2_workaround_str, sh_div_strategy, boardtype, osruntime): Likewise.
(arith_reg_dest): Allow paradoxical DImode subreg for ! TARGET_SHMEDIA.
* sh.h (TARGET_CPU_CPP_BUILTINS): Define __SH_FPU_ANY__ and
__SH_FPU_DOUBLE__.
(INDEXED_ADDRESS_BIT, ADJUST_UNROLL_BIT, TARGET_DIVIDE_INV): Define.
(TARGET_HARVARD): Also true for TARGET_SH5.
(TARGET_DIVIDE_FP, TARGET_DIVIDE_INV_FP, TARGET_DIVIDE_CALL2): Define.
(TARGET_DIVIDE_INV_MINLAT, TARGET_DIVIDE_INV20U): Define.
(TARGET_DIVIDE_INV20L, TARGET_DIVIDE_INV_CALL): Define.
(TARGET_DIVIDE_INV_CALL2, TARGET_ALLOW_INDEXED_ADDRESS): Define.
(TARGET_ADJUST_UNROLL, TARGET_OPT_DEFAULT, SUBTARGET_OPTIONS): Define.
(TARGET_SWITCHES): Removed excessive whitespace. Added options
indexed-addressing, no-indexed-addressing, adjust-unroll and
no-adjust-unroll.
(TARGET_DEFAULT): Add TARGET_OPT_DEFAULT.
(TARGET_OPTIONS): Define.
(EXTRA_SPECS): Add subtarget_asm_spec.
(SH_ASM_SPEC): Pass cut2-workaround option.
(SUBTARGET_ASM_ISA_SPEC): Enforce STRICT_NOFPU for SH4 --without-fp.
(LINK_EMUL_PREFIX): If target defaults to little endian, default to shl.
(OPTIMIZATION_OPTIONS): Set sh_div_str. If not using if not -mieee,
set flag_finite_math_only.
(sh_divide_strategy_e): New enum.
(sh_div_strategy): Declare.
(OVERRIDE_OPTIONS): Don't set FMOVD_BIT for TARGET_SHCOMPACT.
Clear flag_if_conversion2 for SHMEDIA.
Set sh_div_strategy.
Leave profile_flag and profile_arc_flag alone.
(LOOP_ALIGN): Replace TARGET_HARVARD test with TARGET_HARD_SH4 test.
(HARD_REGNO_MODE_OK): Allow TImode in aligned FP registers.
(MODES_TIEABLE_P): For TARGET_SHMEDIA, allow tying of integral modes
of the same size.
(CONST_OK_FOR_I): Fix detection of I06 constraint.
(PREFERRED_RELOAD_CLASS): Also choose GENERAL_REGS for
PIC_DIRECT_ADDR_P.
(SECONDARY_INPUT_RELOAD_CLASS): Fix parentheses. For TARGET_SHMEDIA,
check for inqhi_operand, LABEL_REF and PIC_DIRECT_ADDR_P.
(FUNCTION_VALUE, PROMOTE_MODE): Don't promote from SImode. For
TARGET_SHMEDIA32, promote to SImode.
(EXTRA_CONSTRAINT_C16): Allow SIGN_EXTEND to SImode.
(DATALABEL_REF_NO_CONST_P: Don't allow SYMBOL_REF.
(DATALABEL_REF_P): Don't define.
(NON_PIC_REFERENCE_P): Allow LABEL_REF and SYMBOL_REF directly inside
a CONST. Don't allow DATALABEL_REF_NO_CONST_P outside of a CONST.
Allow a LABEL_REF in a sum.
(BASE_REGISTER_RTX_P): Check TRULY_NOOP_TRUNCATION.
(INDEX_REGISTER_RTX_P): Likewise.
(GO_IF_LEGITIMATE_INDEX): Check if pased the address of an unaligned
load / store.
(ALLOW_INDEXED_ADDRESS): Define.
(GO_IF_LEGITIMATE_ADDRESS): Use it.
(TRULY_NOOP_TRUNCATION): Don't allow no-op truncation from 64 bit or
beyond to less than 64 bit.
(PRINT_OPERAND_PUNCT_VALID_P): Allow '>'.
(rtx_equal_function_value_matters): Don't declare.
(arith_reg_operand): Allow sign_extend.
(PREDICATE_CODES): Allow SIGN_EXTEND in arith_reg_operand. Add
any_arith_reg_dest, cache_address_operand, cmp_operand,
fp_arith_reg_dest, logical_operator, logical_reg_operand,
minuend_operand, shift_count_operand, shift_count_reg_operand,
shift_operator, ua_address_operand, ua_offset, unary_float_operator,
xor_operand. Don't allow PARALLEL in sh_1el_vec and sh_rep_vec
Remove shmedia_6bit_operand.
(SPECIAL_MODE_PREDICATES): Add any-arith_reg_dest, target_operand
and target_reg_operand.
(SIDI_OFF, SIMULTANEOUS_PREFETCHES, high_life_started): Define.
(sh_multcost_str, sh_gettrcost_str, sh_div_str): Declare.
(cut2_workaround_str): Declare.
(INDEX_REG_CLASS): Is NO_REGS if ALLOW_INDEXED_ADDRESS is zero.
(LEGITIMIZE_RELOAD_ADDRESS): Check ALLOW_INDEXED_ADDRESS.
Substitute INDEX_REG_CLASS with R0_REGS.
* sh.md (UNSPEC_DIV_INV_M0, UNSPEC_DIV_INV_M1): New constants.
(UNSPEC_DIV_INV_M2, UNSPEC_DIV_INV_M3, UNSPEC_DIV_INV20): Likewise.
(UNSPEC_ASHIFTRT, UNSPEC_THUNK): Likewise.
(Attribute "length"): jump_media has length 8 if
TARGET_SH5_CUT2_WORKAROUND is true.
("highpart"): New attribute.
(cmpsi): Allow TARGET_SHMEDIA.
(cmpeqsi_media, cmpgtsi_media, cmpgtusi_media): New patterns.
(cmpsieqsi_media, cmpsieqdi_media, cmpsigtsi_media): Likewise.
(cmpsigtdi_media, cmpsigtusi_media, cmpsigtudi_media): Likewise.
(*cmpne0si_media, *cmpne0sisi_media, movdicc_true+1): Likewise.
(movdicc_true+2, movsicc_false, movsicc_true): Likewise.
(movsicc_true+1, movsicc_true+2, movsicc_true+3): Likewise.
(*movsicc_umin, movsicc, movqicc, *adddisi3_media): Likewise.
(addsidi3_media, subdisi3_media, mov_neg_si_t): Likewise.
(*subsi3_media+1, *subsi3_media+2, divsi3_media_2): Likewise.
(divsi_inv_call, *divsi_inv_call_combine, divsi_inv_m0): Likewise.
(divsi_inv_m1, divsi_inv_m2, divsi_inv_m3, divsi_inv_m1_3): Likewise.
(divsi_inv20, divsi_inv_fp, *divsi_inv_fp_combine, muldi3): Likewise.
(*andsi3_media, andcsi3): Likewise.
(cmpeqdi_media): Use cmp_operand operand predicate.
(*adddi3_media, adddi3z_media): Use arith_reg_dest operand predicate.
(adddi3_compact, adddi3_compact+1, addc, addc1): Likewise.
(addsi3_media, *addsi3_compact, *subdi3_media): Likewise.
(subdi3_compact, subdi3_compact+1, subc, subc1): Likewise.
(*subsi3_internal, *subsi3_media, udivsi3_sh2a, divsi3_sh2a): Likewise.
(mul_r, mulsidi3_media, mulsidi3_compact): Likewise.
(mulsidi3_compact+1, umulsidi3_media, umulsidi3_compact): Likewise.
(umulsidi3_compact+1, *andsi3_compact, anddi3, andcdi3): Likewise.
(*subsi3_media): Make define_insn_and_split. Use minuend_operand
operand predicate.
(subsi3): Don't force operand 1 into a register if it is a SUBREG.
(udivsi3_i1_media, udivsi3): Use Pmode for function/target address.
(divsi3_i1_media, beq_media, *beq_media_i, bne_media): Likewise.
(bgt_media, bge_media, bgtu_media, bgeu_media, *bgt_media_i): Likewise.
(*blt_media_i, bunordered, jump_media, jump, call_media): Likewise.
(call_value_media, call, call_value, sibcall_media, sibcall): Likewise.
(indirect_jump, casesi_jump_media, GOTaddr2picreg, *ptb): Likewise.
(symGOT_load, casesi, casesi_shift_media, casesi_load_media): Likewise.
(return_media_i, return_media): Likewise.
(udivsi3_i1_media): Enable also for ! TARGET_DIVIDE_FP.
(divsi3_i1_media): Likewise. Don't clobber R2 / R3 / TR1 / TR2.
(divsi3): Add support for division by multiplying with inverse.
(andsi3): Use logical_reg_operand predicate. Add SHmedia support.
(iorsi3): Rename to:
(*iorsi3_compact).
(xorsi3): Rename to:
(*xorsi3_compact).
(iorsi3, *iorsi3_media, *logical_sidi3, xorsi3): New patterns.
(*logical_sidisi3, *logical_sidi3_2, rotrdi3_mextr+1): Likewise.
(ashrsi2_31+2, *ashlsi_c_void, *ashldisi3_media): Likewise.
(*lshrdisi3_media, *ashrdisi3_media, ashrdisi3_media_high): Likewise.
(ashrdisi3_media_opaque, one_cmpldi2+1, cneg, movsi_const): Likewise.
(movsi_const_16bit, *movdi_media_I16, *shori_media_si): Likewise.
(*beq_media_i32, *bgt_media_i32, *blt_media_i32): Likewise.
(bunordered+1, sibcalli_thunk, ptrel_si, cmpsieqsf_media): Likewise.
(cmpsieqdf_media, addv2hi3, ashlv2si3+1, subv2hi3, ldhi_l): Likewise.
(ldhi_q, *ldhi_q_comb0, *ldhi_q_comb1, ldlo_l, ldlo_q): Likewise.
(*ldlo_q_comb0, *ldlo_q_comb1, sthi_l, sthi_q): Likewise.
(*sthi_q_comb0, *sthi_q_comb1, stlo_l, stlo_q): Likewise.
(*stlo_q_comb0, *stlo_q_comb1, ldhi_l64, ldhi_q64, ldlo_l64): Likewise.
(ldlo_q64, sthi_l64, sthi_q64, stlo_l64, stlo_q64, alloco_i): Likewise.
(alloca_i+1): Likewise.
(prefetch_media): Inhibit generator function generation.
(prefetch_i4): Likewise. Also enable for TARGET_SHCOMPACT.
(*iorsi3_compact, iordi3): Use arith_reg_dest operand predicate.
(*xorsi3_compact, xordi3, xordi3+1, rotlsi3_1, rotlsi3_31): Likewise.
(rotlsi3_16, rotlsi3, *rotlhi3_8, ashlsi3_sh2a, ashlsi3_std): Likewise.
(ashlhi3_k, ashlsi3_n, ashlsi3_n+1, ashlsi3_media): Likewise.
(*ashlhi3_n, ashlhi3+1, ashrsi3_sh2a, ashrsi3_k, ashrsi2_16): Likewise.
(ashrsi2_16+1, ashrsi2_31, ashrsi2_31+1, ashlsi_c): Likewise.
(ashrsi3_d, ashrsi3_media, lshrsi3_sh2a, lshrsi3_d): Likewise.
(lshrsi3_m, lshrsi3_k, lshrsi3_n, lshrsi3_n, lshrsi3_media): Likewise.
(lshrsi3, ashldi3_k, ashldi3_mediai, lshrdi3_k): Likewise.
(ashrdi3_k, xtrct_left, xtrct_right, negc, *negdi_media): Likewise.
(negsi2, one_cmplsi2, one_cmpldi2, zero_extendsidi2): Likewise.
(*zero_extendhisi2_compact, *zero_extendqisi2_compact): Likewise.
(zero_extendqihi2, extendhisi2, *extendhisi2_compact): Likewise.
(extendqisi2, *extendqisi2_compact, extendqihi2): Likewise.
(movsi_const_16bit+1, *movdi_media_I16+1): Likewise.
(movdf_media_nofpu+1, movsf_media_nofpu+1, dect, movt, seq): Likewise.
(movnegt+1, divsf3_i): Likewise.
(xordi3): Use xor_operand operand predicate.
(ashlsi3_media): Use shift_count_operand operand predicate.
(ashrsi3_media, lshrsi3_media, ashldi3_media, lshrdi3_media): Likewise.
(ashrdi3_media): Likewise.
(ashrsi2_31+1): Use mov_neg_si_t.
(lshrdi3_media, ashrdi3_media): Use ext_dest_operand predicate.
Make sure that either the destination is not a subreg, or that the
shift generates a sufficient number of sign bit copies.
(*loaddi_trunc): Use any_register_operand predicate.
(ic_invalidate_line_sh4a): Likewise.
(*zero_extendhisi2_media+1): Use simplify_gen_subreg.
(*extendhisi2_media+1i, *extendqisi2_media+1): Likewise.
(extendsidi2): Add fmov.sl alternative.
(load_ra): Add mode for operand 1.
(*movsi_media): Discourage the use of floating point registers.
Allow TRUNCATE.
(*movsi_media_nofpu): Ignore target register alternative for register
preferencing. Allow TRUNCATE.
(movsi_const_16bit+1): Use gen_movsi_const, and add an REG_EQUAL note.
(*movqi_media): Use extend_reg_or_0_operand predicate.
(*movdi_media): Ignore target register alternative for register
preferencing. Discourage the use of floating point registers.
(*movdi_media_nofpu): Ignore target register alternative for register
preferencing.
(movdi_const_16bit+1): If the source is subregged from SImode,
sign-extend highpart. Use ext_dest_operand predicate.
(movdi_const_16bit+2, shori_media): Use ext_dest_operand predicate.
(reload_outdf+7, reload_outdf+8): Check ALLOW_INDEXED_ADDRESS.
(stuff_delay_slot): Add modes for operands 0 and 1.
(*beq_media_i, *bgt_media_i): Add '>' to output templates.
(*blt_media_i, jump_media): Likewise.
(beq, bne): Pass through SImode inputs, and I06 constants.
(bgt, blt, ble, bge, bgtu): Pass through SImode inputs, the constant 0.
(bltu, bgeu, bleu): Likewise.
(GOTaddr2picreg): Don't call gen_datalabel_ref.
(ptrel): Rename to:
(ptrel_di).
(tls_global_dynamic, tls_local_dynamic): Add mode for call.
(seq): Properly support input modes other than DImode.
(slt, sle, sgt, sge,sne): Properly support SImode.
(addsf3_i, negdf2_i, sqrtdf2_i, absdf2_i): Use fp_arith_reg_operand.
(mac_media) Enable generator function generation.
(fix_truncsfdi2): Use fp_arith_reg_dest operand predicate.
(fix_truncdfdi2): Likewise.
(movv8qi_i+3): Enable for CONST0_RTX too.
(movv2hi_i): Use add.l, not addz.l.
(ashlv2si3, ashlv4hi3, lshrv2si3): Use shift_count_reg_operand.
(lshrv4hi3): Likewise.
(ussubv8qi3): Allow zero for operand 1.
(prefetch): Allow any mode for operand 0. Enable for SHCOMPACT.
Use force_reg.
* config/sh/shmedia.md: (shmedia): Remove automaton declaration.
(sh5inst_pipe, sh5fpu_pipe): New automatons.
(sh5issue): Use sh5inst_pipe.
(sh5fds): Use sh5fpu_pipe.
(shmedia_fdiv, shmedia_dfdiv): Also use sh5issue.
* config/sh/sshmedia.h (sh_media_GETCON, sh_media_PUTCON): Declare
with always_inline Attribute.
* t-sh64 (LIB1ASMFUNCS): Add _div_table.
* config/sh/ushmedia.h (sh_media_MABS_L): Use builtin function.
(sh_media_MABS_W, sh_media_MADD_L, sh_media_MADD_W): Likewise.
(sh_media_MADDS_L, sh_media_MADDS_UB, sh_media_MADDS_W): Likewise.
(sh_media_MCMPEQ_B, sh_media_MCMPEQ_L, sh_media_MCMPEQ_W): Likewise.
(sh_media_MCMPGT_UB, sh_media_MCMPGT_L, sh_media_MCMPGT_W): Likewise.
(sh_media_MCMV, sh_media_MCNVS_LW, sh_media_MCNVS_WB): Likewise.
(sh_media_MCNVS_WUB, sh_media_MEXTR1, sh_media_MEXTR2): Likewise.
(sh_media_MEXTR3, sh_media_MEXTR4, sh_media_MEXTR5): Likewise.
(sh_media_MEXTR6, sh_media_MEXTR7, sh_media_MMACFX_WL): Likewise.
(sh_media_MMACNFX_WL, sh_media_MMUL_L, sh_media_MMUL_W): Likewise.
(sh_media_MMULFX_L, sh_media_MMULFX_W, sh_media_MMULFXRP_W): Likewise.
(sh_media_MMULHI_WL, sh_media_MMULLO_WL): Likewise.
(sh_media_MMULSUM_WQ, sh_media_MPERM_W, sh_media_MSAD_UBQ): Likewise.
(sh_media_MSHALDS_L, sh_media_MSHALDS_W, sh_media_MSHARD_L): Likewise.
(sh_media_MSHARD_W, sh_media_MSHARDS_Q, sh_media_MSHFHI_B): Likewise.
(sh_media_MSHFHI_L, sh_media_MSHFHI_W, sh_media_MSHFLO_B): Likewise.
(sh_media_MSHFLO_L, sh_media_MSHFLO_W, sh_media_MSHLLD_L): Likewise.
(sh_media_MSHLLD_W, sh_media_MSHLRD_L, sh_media_MSHLRD_W): Likewise.
(sh_media_MSUB_L, sh_media_MSUB_W, sh_media_MSUBS_L): Likewise.
(sh_media_MSUBS_UB, sh_media_MSUBS_W, sh_media_FABS_D): Likewise.
(sh_media_FABS_S, sh_media_FCMPUN_D, sh_media_FCMPUN_S): Likewise.
(sh_media_FIPR_S, sh_media_FMAC_S, sh_media_FSQRT_D): Likewise.
(sh_media_FSQRT_S, sh_media_FTRV_S, sh_media_LDHI_L): Likewise.
(sh_media_LDHI_Q, sh_media_LDLO_L, sh_media_LDLO_Q): Likewise.
(sh_media_STHI_L, sh_media_STHI_Q, sh_media_STLO_L): Likewise.
(sh_media_STLO_Q, sh_media_NSB, sh_media_BYTEREV): Likewise.
(sh_media_PREFO, sh_media_ALLOCO): Likewise.
(sh_media_FCOSA_S, sh_media_FSINA_S): New function.
(sh_media_FMOV_DQ, sh_media_FMOV_LS): Use union assignment.
(sh_media_FMOV_QD, sh_media_FMOV_SL): Likewise.
(sh_media_CMVEQ): Use C code. Add attribute always_inline.
(sh_media_CMVNE): Likewise.
(sh_media_ADDZ_L): Use C code.
(sh_media_unaligned_LD_L): Use intrinsics directly.
(sh_media_unaligned_LD_Q, sh_media_unaligned_ST_L): Likewise.
(sh_media_unaligned_ST_Q): Likewise.
* config/sh/divtab.c: New file.
2005-04-06 Andrew Stubbs <andrew.stubbs@superh.com>
J"orn Rennecke <joern.rennecke@superh.com>
* config/sh/superh64.h, config/sh/superh.h: New files.
* config/sh/newlib.h, config/sh/t-superh: Likewise.
* config.gcc: Add support for sh*-superh-elf* and sh64-superh-linux*.
gcc/testsuite:
2005-05-06 J"orn Rennecke <joern.rennecke@st.com>
* gcc.dg/pr15784-3.c: Add -fno-finite-math-only option.
* gcc.dg/20021029-1.c: For sh64*-*-*, add -mpt-fixed.
From-SVN: r99460
2005-05-09 17:42:55 +00:00
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#endif /* L_div_table */
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2006-06-13 17:44:56 +00:00
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#ifdef L_udiv_qrnnd_16
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HIDDEN_FUNC(GLOBAL(udiv_qrnnd_16))
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/* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */
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/* n1 < d, but n1 might be larger than d1. */
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.global GLOBAL(udiv_qrnnd_16)
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.balign 8
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GLOBAL(udiv_qrnnd_16):
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div0u
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cmp/hi r6,r0
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bt .Lots
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.rept 16
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div1 r6,r0
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.endr
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extu.w r0,r1
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bt 0f
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add r6,r0
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0: rotcl r1
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mulu.w r1,r5
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xtrct r4,r0
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swap.w r0,r0
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sts macl,r2
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cmp/hs r2,r0
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sub r2,r0
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bt 0f
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addc r5,r0
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add #-1,r1
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bt 0f
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1: add #-1,r1
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rts
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add r5,r0
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.balign 8
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.Lots:
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sub r5,r0
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swap.w r4,r1
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xtrct r0,r1
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clrt
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mov r1,r0
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addc r5,r0
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mov #-1,r1
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SL1(bf, 1b,
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shlr16 r1)
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0: rts
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nop
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ENDFUNC(GLOBAL(udiv_qrnnd_16))
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#endif /* L_udiv_qrnnd_16 */
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