Update verilog-mode.el
* verilog-mode.el (verilog-read-decls, verilog-calc-1): Fix "default clocking" indentation and preventing AUTOs from working, bug1084. Reported by Alan Morgan. (verilog-diff-report): Fix `verilog-diff-report' not returning bad status on differences, bug1087. Reported by Eric Jackowski. (verilog-auto-inst-param-value) (verilog-auto-inst-param-value-type, verilog-read-sub-decls) (verilog-read-sub-decls-expr, verilog-read-sub-decls-gate) (verilog-read-sub-decls-line, verilog-read-sub-decls-sig) (verilog-read-sub-decls-type): When `verilog-auto-inst-param-value-type' is set, which is now the default, AUTOINPUT etc will now substitute parameter types from submodules, bug1061. Reported by Brad Dobbie. (verilog-auto-reset, verilog-backward-case-item) (verilog-extended-case-re, verilog-read-always-signals-recurse): Fix indentation of randcase, bug1072. Reported by David Rogoff. (verilog-read-sub-decls-expr) (verilog-sig-multidim-string): Fix AUTOINST ordering of dimensions in generated comments, bug1057. Reported by Kaushal Modi. (verilog-auto-wire-comment, verilog-insert-definition): Add `verilog-auto-wire-comment' to suppress wire comments. Reported by Eric Jackowski. (verilog-extended-complete-re): Fix indentation of class static functions, bug1053. Reported by Gregory Czajkowski. (verilog-module-filenames): Support tramp for finding verilog modules. Reported by Nevada Sanchez.
This commit is contained in:
Wilson Snyder
parent
2f5e0b1bf7
commit
eda171a924
1 changed files with 192 additions and 102 deletions
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@ -123,7 +123,7 @@
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;;
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "2016-03-22-7547e76-vpo-GNU"
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(defconst verilog-mode-version "2016-11-14-26d3540-vpo-GNU"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -753,6 +753,13 @@ mode is experimental."
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:type 'boolean)
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(put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
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(defcustom verilog-auto-wire-comment t
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"Non-nil indicates to insert to/from comments with `verilog-auto-wire' etc."
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:version "25.1"
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:group 'verilog-mode-actions
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:type 'boolean)
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(put 'verilog-auto-wire-comment 'safe-local-variable `verilog-booleanp)
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(defcustom verilog-auto-wire-type nil
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"Non-nil specifies the data type to use with `verilog-auto-wire' etc.
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Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
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@ -1131,32 +1138,67 @@ be replaced, and will remain symbolic.
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For example, imagine a submodule uses parameters to declare the size of its
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inputs. This is then used by an upper module:
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module InstModule (o,i);
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parameter WIDTH;
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input [WIDTH-1:0] i;
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endmodule
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module InstModule (o,i);
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parameter WIDTH;
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input [WIDTH-1:0] i;
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parameter type OUT_t;
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output OUT_t o;
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endmodule
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module ExampInst;
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InstModule
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#(.PARAM(10))
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instName
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(/*AUTOINST*/
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.i (i[PARAM-1:0]));
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module ExampInst;
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs
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output OUT_t o;
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// End of automatics
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Note even though PARAM=10, the AUTOINST has left the parameter as a
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symbolic name. If `verilog-auto-inst-param-value' is set, this will
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InstModule
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#(.WIDTH(10),
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,.OUT_t(upper_t))
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instName
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(/*AUTOINST*/
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.i (i[WIDTH-1:0]),
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.o (o));
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Note even though WIDTH=10, the AUTOINST has left the parameter as
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a symbolic name. Likewise the OUT_t is preserved as the name
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from the instantiated module.
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If `verilog-auto-inst-param-value' is set, this will
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instead expand to:
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module ExampInst;
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InstModule
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#(.PARAM(10))
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instName
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(/*AUTOINST*/
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.i (i[9:0]));"
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs
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output upper_t o;
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// End of automatics
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InstModule
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#(.WIDTH(10),
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,.OUT_t(upper_t))
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instName
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(/*AUTOINST*/
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.i (i[9:0]),
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.o (o));
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Note that the instantiation now has \"i[9:0]\" as the WIDTH
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was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT
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is now upper_t, from the OUT_t parameter override.
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This second expansion of parameter types can be overridden with
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`verilog-auto-inst-param-value-type'."
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:group 'verilog-mode-auto
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:type 'boolean)
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(put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
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(defcustom verilog-auto-inst-param-value-type t
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"Non-nil means expand parameter type in instantiations.
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If nil, leave parameter types as symbolic names.
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See `verilog-auto-inst-param-value'."
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:version "25.1"
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:group 'verilog-mode-auto
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:type 'boolean)
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(put 'verilog-auto-inst-param-value-type 'safe-local-variable 'verilog-booleanp)
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(defcustom verilog-auto-inst-sort nil
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"Non-nil means AUTOINST signals will be sorted, not in declaration order.
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Also affects AUTOINSTPARAM. Declaration order is the default for
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@ -1761,7 +1803,7 @@ so there may be a large up front penalty for the first search."
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(let (pt)
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(while (and (not pt)
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(re-search-forward regexp bound noerror))
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(if (verilog-inside-comment-or-string-p)
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(if (verilog-inside-comment-or-string-p (match-beginning 0))
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(re-search-forward "[/\"\n]" nil t) ; Only way a comment or quote can end
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(setq pt (match-end 0))))
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pt))
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@ -1775,7 +1817,7 @@ so there may be a large up front penalty for the first search."
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(let (pt)
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(while (and (not pt)
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(re-search-backward regexp bound noerror))
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(if (verilog-inside-comment-or-string-p)
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(if (verilog-inside-comment-or-string-p (match-beginning 0))
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(re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
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(setq pt (match-beginning 0))))
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pt))
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@ -2561,15 +2603,15 @@ find the errors."
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"\\|\\(\\<table\\>\\)" ;7
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"\\|\\(\\<specify\\>\\)" ;8
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"\\|\\(\\<function\\>\\)" ;9
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"\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
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"\\|\\(\\<task\\>\\)" ;14
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"\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
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"\\|\\(\\<generate\\>\\)" ;18
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"\\|\\(\\<covergroup\\>\\)" ;16 20
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"\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
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"\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
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"\\|\\(\\<clocking\\>\\)" ;22 27
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"\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
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"\\|\\(\\(?:\\<\\(?:virtual\\|protected\\|static\\)\\>\\s-+\\)*\\<function\\>\\)" ;10
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"\\|\\(\\<task\\>\\)" ;11
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"\\|\\(\\(?:\\<\\(?:virtual\\|protected\\|static\\)\\>\\s-+\\)*\\<task\\>\\)" ;12
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"\\|\\(\\<generate\\>\\)" ;13
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"\\|\\(\\<covergroup\\>\\)" ;14
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"\\|\\(\\(?:\\(?:\\<cover\\>\\s-+\\)\\|\\(?:\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;15
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"\\|\\(\\<\\(?:rand\\)?sequence\\>\\)" ;16
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"\\|\\(\\<clocking\\>\\)" ;17
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"\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;18
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"\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
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;;
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))
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@ -2812,10 +2854,12 @@ find the errors."
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"\\(\\<\\(import\\|export\\)\\>\\s-+\"DPI\\(-C\\)?\"\\s-+\\(\\<\\(context\\|pure\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\<\\(function\\|task\\)\\>\\)"
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))
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(defconst verilog-default-clocking-re "\\<default\\s-+clocking\\>")
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(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
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(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
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(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\|randcase\\)")
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(defconst verilog-extended-complete-re
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(concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
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;; verilog-beg-of-statement also looks backward one token to extend this match
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(concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\|\\<static\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
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"\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
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"\\|\\(\\(\\<\\(import\\|export\\)\\>\\s-+\\)?\\(\"DPI\\(-C\\)?\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\(function\\>\\|task\\>\\)\\)"
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"\\|" verilog-extended-case-re ))
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@ -3584,28 +3628,28 @@ Use filename, if current buffer being edited shorten to just buffer name."
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;; Search forward for matching endfunction
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(setq reg "\\<endfunction\\>" )
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(setq nest 'no))
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((match-end 14)
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((match-end 11)
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;; Search forward for matching endtask
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(setq reg "\\<endtask\\>" )
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(setq nest 'no))
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((match-end 15)
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((match-end 12)
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;; Search forward for matching endtask
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(setq reg "\\<endtask\\>" )
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(setq nest 'no))
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((match-end 19)
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((match-end 12)
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;; Search forward for matching endgenerate
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(setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
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((match-end 20)
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((match-end 13)
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;; Search forward for matching endgroup
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(setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
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((match-end 21)
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((match-end 14)
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;; Search forward for matching endproperty
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(setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
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((match-end 25)
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((match-end 15)
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;; Search forward for matching endsequence
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(setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
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(setq md 3)) ; 3 to get to endsequence in the reg above
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((match-end 27)
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((match-end 17)
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;; Search forward for matching endclocking
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(setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
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(if (and reg
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@ -3884,7 +3928,10 @@ Key bindings specific to `verilog-mode-map' are:
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;;; Integration with the speedbar
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;;
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(declare-function speedbar-add-supported-extension "speedbar" (extension))
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;; Avoid problems with XEmacs byte-compiles.
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;; For GNU Emacs, the eval-after-load will handle if it isn't loaded yet.
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(when (eval-when-compile (fboundp 'declare-function))
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(declare-function speedbar-add-supported-extension "speedbar" (extension)))
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(defun verilog-speedbar-initialize ()
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"Initialize speedbar to understand `verilog-mode'."
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@ -4566,7 +4613,7 @@ Limit search to point LIM."
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(progn
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(if
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(verilog-re-search-backward
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"\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
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"\\<\\(randcase\\|case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
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(progn
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(cond
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((match-end 1)
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@ -5692,13 +5739,17 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
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(goto-char here)
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(throw 'nesting 'block)))))
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((match-end 27) ; *sigh* might be a clocking declaration
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((match-end 17) ; *sigh* might be a clocking declaration
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(let ((here (point)))
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(if (verilog-in-paren)
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t ; this is a normal statement
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(progn ; or is fork, starts a new block
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(goto-char here)
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(throw 'nesting 'block)))))
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(cond ((verilog-in-paren)
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t) ; this is a normal statement
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((save-excursion
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(verilog-beg-of-statement)
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(looking-at verilog-default-clocking-re))
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t) ; default clocking, normal statement
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(t
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(goto-char here) ; or is clocking, starts a new block
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(throw 'nesting 'block)))))
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;; need to consider typedef struct here...
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((looking-at "\\<class\\|struct\\|function\\|task\\>")
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@ -5826,7 +5877,7 @@ Jump from end to matching begin, from endcase to matching case, and so on."
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"\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
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((looking-at "\\<endtask\\>")
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;; 2: Search back for matching task
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(setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
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(setq reg "\\(\\<task\\>\\)\\|\\(\\(\\<\\(virtual\\|protected\\|static\\)\\>\\s-+\\)+\\<task\\>\\)")
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(setq nesting 'no))
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((looking-at "\\<endcase\\>")
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(catch 'nesting
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@ -5848,7 +5899,7 @@ Jump from end to matching begin, from endcase to matching case, and so on."
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(setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
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((looking-at "\\<endfunction\\>")
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;; 8: Search back for matching function
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(setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
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(setq reg "\\(\\<function\\>\\)\\|\\(\\(\\<\\(virtual\\|protected\\|static\\)\\>\\s-+\\)+\\<function\\>\\)")
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(setq nesting 'no))
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;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
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((looking-at "\\<endgenerate\\>")
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@ -6300,7 +6351,7 @@ Return >0 for nested struct."
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(let ((p (point)))
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(and
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(equal (char-after) ?\{)
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(forward-list)
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(ignore-errors (forward-list))
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(progn (backward-char 1)
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(verilog-backward-ws&directives)
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(and
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@ -7831,7 +7882,7 @@ See also `verilog-sk-header' for an alternative format."
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(if (verilog-sig-multidim sig)
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(let ((str "") (args (verilog-sig-multidim sig)))
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(while args
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(setq str (concat str (car args)))
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(setq str (concat (car args) str))
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(setq args (cdr args)))
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str)))
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(defsubst verilog-sig-modport (sig)
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@ -8352,7 +8403,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
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in-modport in-clocking in-ign-to-semi ptype ign-prop
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sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
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sigs-gparam sigs-intf sigs-modports
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vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
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vec expect-signal keywd last-keywd newsig rvalue enum io
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signed typedefed multidim
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modport
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varstack tmp)
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;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
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@ -8433,7 +8485,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
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;; Normal or escaped identifier -- note we remember the \ if escaped
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((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
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(goto-char (match-end 0))
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(setq keywd (match-string-no-properties 1))
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(setq last-keywd keywd
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keywd (match-string-no-properties 1))
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(when (string-match "^\\\\" (match-string 1))
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(setq keywd (concat keywd " "))) ; Escaped ID needs space at end
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;; Add any :: package names to same identifier
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@ -8498,7 +8551,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
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(setq functask (1- functask)))
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((equal keywd "modport")
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(setq in-modport t))
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((equal keywd "clocking")
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((and (equal keywd "clocking")
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(not (equal last-keywd "default")))
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(setq in-clocking t))
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((equal keywd "import")
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(if v2kargs-ok ; import in module header, not a modport import
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@ -8623,12 +8677,20 @@ Return an array of [outputs inouts inputs wire reg assign const]."
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(defvar create-lockfiles)
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(defvar which-func-modes))
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|
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(defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim mem)
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(defun verilog-read-sub-decls-type (par-values portdata)
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"For `verilog-read-sub-decls-line', decode a signal type."
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(let* ((type (verilog-sig-type portdata))
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(pvassoc (assoc type par-values)))
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(cond ((member type '("wire" "reg")) nil)
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(pvassoc (nth 1 pvassoc))
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(t type))))
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(defun verilog-read-sub-decls-sig (submoddecls par-values comment port sig vec multidim mem)
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"For `verilog-read-sub-decls-line', add a signal."
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;; sig eq t to indicate .name syntax
|
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;;(message "vrsds: %s(%S)" port sig)
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(let ((dotname (eq sig t))
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portdata)
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portdata)
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(when sig
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(setq port (verilog-symbol-detick-denumber port))
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(setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
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|
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@ -8647,8 +8709,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
|
|||
mem
|
||||
nil
|
||||
(verilog-sig-signed portdata)
|
||||
(unless (member (verilog-sig-type portdata) '("wire" "reg"))
|
||||
(verilog-sig-type portdata))
|
||||
(verilog-read-sub-decls-type par-values portdata)
|
||||
multidim nil)
|
||||
sigs-inout)))
|
||||
((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
|
||||
|
|
@ -8666,8 +8727,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
|
|||
;; Also for backwards compatibility we don't propagate
|
||||
;; "input wire" upwards.
|
||||
;; See also `verilog-signals-edit-wire-reg'.
|
||||
(unless (member (verilog-sig-type portdata) '("wire" "reg"))
|
||||
(verilog-sig-type portdata))
|
||||
(verilog-read-sub-decls-type par-values portdata)
|
||||
multidim nil)
|
||||
sigs-out)))
|
||||
((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
|
||||
|
|
@ -8680,8 +8740,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
|
|||
mem
|
||||
nil
|
||||
(verilog-sig-signed portdata)
|
||||
(unless (member (verilog-sig-type portdata) '("wire" "reg"))
|
||||
(verilog-sig-type portdata))
|
||||
(verilog-read-sub-decls-type par-values portdata)
|
||||
multidim nil)
|
||||
sigs-in)))
|
||||
((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
|
||||
|
|
@ -8693,7 +8752,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
|
|||
mem
|
||||
nil
|
||||
(verilog-sig-signed portdata)
|
||||
(verilog-sig-type portdata)
|
||||
(verilog-read-sub-decls-type par-values portdata)
|
||||
multidim nil)
|
||||
sigs-intf)))
|
||||
((setq portdata (and verilog-read-sub-decls-in-interfaced
|
||||
|
|
@ -8706,13 +8765,13 @@ Return an array of [outputs inouts inputs wire reg assign const]."
|
|||
mem
|
||||
nil
|
||||
(verilog-sig-signed portdata)
|
||||
(verilog-sig-type portdata)
|
||||
(verilog-read-sub-decls-type par-values portdata)
|
||||
multidim nil)
|
||||
sigs-intf)))
|
||||
;; (t -- warning pin isn't defined.) ; Leave for lint tool
|
||||
)))))
|
||||
|
||||
(defun verilog-read-sub-decls-expr (submoddecls comment port expr)
|
||||
(defun verilog-read-sub-decls-expr (submoddecls par-values comment port expr)
|
||||
"For `verilog-read-sub-decls-line', parse a subexpression and add signals."
|
||||
;;(message "vrsde: `%s'" expr)
|
||||
;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
|
||||
|
|
@ -8728,7 +8787,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
|
|||
(let ((mlst (split-string (match-string 1 expr) "[{},]"))
|
||||
mstr)
|
||||
(while (setq mstr (pop mlst))
|
||||
(verilog-read-sub-decls-expr submoddecls comment port mstr)))))
|
||||
(verilog-read-sub-decls-expr submoddecls par-values comment port mstr)))))
|
||||
(t
|
||||
(let (sig vec multidim mem)
|
||||
;; Remove leading reduction operators, etc
|
||||
|
|
@ -8751,16 +8810,16 @@ Return an array of [outputs inouts inputs wire reg assign const]."
|
|||
(setq vec (match-string 1 expr)
|
||||
expr (substring expr (match-end 0))))
|
||||
;; Find .[unpacked_memory] or .[unpacked][unpacked]...
|
||||
(while (string-match "^\\s-*\\.\\(\\[[^]]+\\]\\)" expr)
|
||||
(while (string-match "^\\s-*\\.\\(\\(\\[[^]]+\\]\\)+\\)" expr)
|
||||
;;(message "vrsde-m: `%s'" (match-string 1 expr))
|
||||
(setq mem (match-string 1 expr)
|
||||
expr (substring expr (match-end 0))))
|
||||
;; If found signal, and nothing unrecognized, add the signal
|
||||
;;(message "vrsde-rem: `%s'" expr)
|
||||
(when (and sig (string-match "^\\s-*$" expr))
|
||||
(verilog-read-sub-decls-sig submoddecls comment port sig vec multidim mem))))))
|
||||
(verilog-read-sub-decls-sig submoddecls par-values comment port sig vec multidim mem))))))
|
||||
|
||||
(defun verilog-read-sub-decls-line (submoddecls comment)
|
||||
(defun verilog-read-sub-decls-line (submoddecls par-values comment)
|
||||
"For `verilog-read-sub-decls', read lines of port defs until none match.
|
||||
Inserts the list of signals found, using submodi to look up each port."
|
||||
(let (done port)
|
||||
|
|
@ -8778,13 +8837,13 @@ Inserts the list of signals found, using submodi to look up each port."
|
|||
;; .name
|
||||
((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
|
||||
(verilog-read-sub-decls-sig
|
||||
submoddecls comment (match-string-no-properties 1) t ; sig==t for .name
|
||||
submoddecls par-values comment (match-string-no-properties 1) t ; sig==t for .name
|
||||
nil nil nil) ; vec multidim mem
|
||||
(setq port nil))
|
||||
;; .\escaped_name
|
||||
((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
|
||||
(verilog-read-sub-decls-sig
|
||||
submoddecls comment (concat (match-string-no-properties 1) " ") t ; sig==t for .name
|
||||
submoddecls par-values comment (concat (match-string-no-properties 1) " ") t ; sig==t for .name
|
||||
nil nil nil) ; vec multidim mem
|
||||
(setq port nil))
|
||||
;; random
|
||||
|
|
@ -8799,28 +8858,29 @@ Inserts the list of signals found, using submodi to look up each port."
|
|||
(when port
|
||||
(cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
|
||||
(verilog-read-sub-decls-sig
|
||||
submoddecls comment port
|
||||
submoddecls par-values comment port
|
||||
(verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
|
||||
nil nil nil)) ; vec multidim mem
|
||||
;;
|
||||
((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
|
||||
(verilog-read-sub-decls-sig
|
||||
submoddecls comment port
|
||||
submoddecls par-values comment port
|
||||
(verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
|
||||
(match-string-no-properties 2) nil nil)) ; vec multidim mem
|
||||
;; Fastpath was above looking-at's.
|
||||
;; For something more complicated invoke a parser
|
||||
((looking-at "[^)]+")
|
||||
(verilog-read-sub-decls-expr
|
||||
submoddecls comment port
|
||||
submoddecls par-values comment port
|
||||
(buffer-substring-no-properties
|
||||
(point) (1- (progn (search-backward "(") ; start at (
|
||||
(verilog-forward-sexp-ign-cmt 1)
|
||||
(point)))))))) ; expr
|
||||
;;
|
||||
(forward-line 1)))))
|
||||
;;(verilog-read-sub-decls-line (verilog-subdecls-new nil nil nil nil nil) nil "Cmt")
|
||||
|
||||
(defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
|
||||
(defun verilog-read-sub-decls-gate (submoddecls par-values comment submod end-inst-point)
|
||||
"For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
|
||||
Inserts the list of signals found."
|
||||
(save-excursion
|
||||
|
|
@ -8844,7 +8904,7 @@ Inserts the list of signals found."
|
|||
(setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
|
||||
iolist (cdr iolist))
|
||||
(verilog-read-sub-decls-expr
|
||||
submoddecls comment "primitive_port"
|
||||
submoddecls par-values comment "primitive_port"
|
||||
(match-string 0)))
|
||||
(t
|
||||
(forward-char 1)
|
||||
|
|
@ -8870,13 +8930,16 @@ Outputs comments above subcell signals, for example:
|
|||
.in (in));"
|
||||
(save-excursion
|
||||
(let ((end-mod-point (verilog-get-end-of-defun))
|
||||
st-point end-inst-point
|
||||
st-point end-inst-point par-values
|
||||
;; below 3 modified by verilog-read-sub-decls-line
|
||||
sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
|
||||
(verilog-beg-of-defun-quick)
|
||||
(while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
|
||||
(save-excursion
|
||||
(goto-char (match-beginning 0))
|
||||
(setq par-values (and verilog-auto-inst-param-value
|
||||
verilog-auto-inst-param-value-type
|
||||
(verilog-read-inst-param-value)))
|
||||
(unless (verilog-inside-comment-or-string-p)
|
||||
;; Attempt to snarf a comment
|
||||
(let* ((submod (verilog-read-inst-module))
|
||||
|
|
@ -8894,7 +8957,7 @@ Outputs comments above subcell signals, for example:
|
|||
(point))
|
||||
st-point (point))
|
||||
(forward-char 1)
|
||||
(verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
|
||||
(verilog-read-sub-decls-gate submoddecls par-values comment submod end-inst-point))
|
||||
;; Non-primitive
|
||||
(t
|
||||
(when (setq submodi (verilog-modi-lookup submod t))
|
||||
|
|
@ -8908,19 +8971,19 @@ Outputs comments above subcell signals, for example:
|
|||
;; However I want it to be runnable even on user's manually added signals
|
||||
(let ((verilog-read-sub-decls-in-interfaced t))
|
||||
(while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
|
||||
(verilog-read-sub-decls-line submoddecls comment))) ; Modifies sigs-ifd
|
||||
(verilog-read-sub-decls-line submoddecls par-values comment))) ; Modifies sigs-ifd
|
||||
(goto-char st-point)
|
||||
(while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
|
||||
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
|
||||
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-out
|
||||
(goto-char st-point)
|
||||
(while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
|
||||
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
|
||||
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-out
|
||||
(goto-char st-point)
|
||||
(while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
|
||||
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-inout
|
||||
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-inout
|
||||
(goto-char st-point)
|
||||
(while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
|
||||
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-in
|
||||
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-in
|
||||
)))))))
|
||||
;; Combine duplicate bits
|
||||
;;(setq rr (vector sigs-out sigs-inout sigs-in))
|
||||
|
|
@ -9111,7 +9174,7 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
|
|||
;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
|
||||
(setq ignore-next nil rvalue semi-rvalue)
|
||||
(if (not exit-keywd) (setq end-else-check t)))
|
||||
((member keywd '("case" "casex" "casez"))
|
||||
((member keywd '("case" "casex" "casez" "randcase"))
|
||||
(skip-syntax-forward "w_")
|
||||
(verilog-read-always-signals-recurse "endcase" t nil)
|
||||
(setq ignore-next nil rvalue semi-rvalue)
|
||||
|
|
@ -9337,29 +9400,43 @@ Optionally associate it with the specified enumeration ENUMNAME."
|
|||
If the filename is provided, `verilog-library-flags' will be used to
|
||||
resolve it. If optional RECURSE is non-nil, recurse through \\=`includes.
|
||||
|
||||
Parameters must be simple assignments to constants, or have their own
|
||||
\"parameter\" label rather than a list of parameters. Thus:
|
||||
Localparams must be simple assignments to constants, or have their own
|
||||
\"localparam\" label rather than a list of localparams. Thus:
|
||||
|
||||
parameter X = 5, Y = 10; // Ok
|
||||
parameter X = {1\\='b1, 2\\='h2}; // Ok
|
||||
parameter X = {1\\='b1, 2\\='h2}, Y = 10; // Bad, make into 2 parameter lines
|
||||
localparam X = 5, Y = 10; // Ok
|
||||
localparam X = {1\\='b1, 2\\='h2}; // Ok
|
||||
localparam X = {1\\='b1, 2\\='h2}, Y = 10; // Bad, make into 2 localparam lines
|
||||
|
||||
Defines must be simple text substitutions, one on a line, starting
|
||||
at the beginning of the line. Any ifdefs or multiline comments around the
|
||||
define are ignored.
|
||||
|
||||
Defines are stored inside Emacs variables using the name vh-{definename}.
|
||||
Defines are stored inside Emacs variables using the name
|
||||
vh-{definename}.
|
||||
|
||||
This function is useful for setting vh-* variables. The file variables
|
||||
feature can be used to set defines that `verilog-mode' can see; put at the
|
||||
*END* of your file something like:
|
||||
Localparams define what symbols are constants so that AUTOSENSE
|
||||
will not include them in sensitivity lists. However any
|
||||
parameters in the include file are not considered ports in the
|
||||
including file, thus will not appear in AUTOINSTPARAM lists for a
|
||||
parent module..
|
||||
|
||||
The file variables feature can be used to set defines that
|
||||
`verilog-mode' can see; put at the *END* of your file something
|
||||
like:
|
||||
|
||||
// Local Variables:
|
||||
// vh-macro:\"macro_definition\"
|
||||
// End:
|
||||
|
||||
If macros are defined earlier in the same file and you want their values,
|
||||
you can read them automatically (provided `enable-local-eval' is on):
|
||||
you can read them automatically with:
|
||||
|
||||
// Local Variables:
|
||||
// verilog-auto-read-includes:t
|
||||
// End:
|
||||
|
||||
Or a more specific alternative example, which requires haing
|
||||
`enable-local-eval' non-nil:
|
||||
|
||||
// Local Variables:
|
||||
// eval:(verilog-read-defines)
|
||||
|
|
@ -9426,6 +9503,13 @@ file.
|
|||
|
||||
It is often useful put at the *END* of your file something like:
|
||||
|
||||
// Local Variables:
|
||||
// verilog-auto-read-includes:t
|
||||
// End:
|
||||
|
||||
Or the equivalent longer version, which requires having
|
||||
`enable-local-eval' non-nil:
|
||||
|
||||
// Local Variables:
|
||||
// eval:(verilog-read-defines)
|
||||
// eval:(verilog-read-includes)
|
||||
|
|
@ -9848,9 +9932,14 @@ Uses the CURRENT filename, `verilog-library-extensions',
|
|||
`verilog-library-directories' and `verilog-library-files'
|
||||
variables to build the path."
|
||||
;; Return search locations for it
|
||||
(append (list current) ; first, current buffer
|
||||
(verilog-library-filenames module current t)
|
||||
verilog-library-files)) ; finally, any libraries
|
||||
(append (list current) ; first, current buffer
|
||||
(verilog-library-filenames module current t)
|
||||
;; Finally any libraries; fixed up if using e.g. tramp
|
||||
(mapcar (lambda (fname)
|
||||
(if (file-name-absolute-p fname)
|
||||
(concat (file-remote-p current) fname)
|
||||
fname))
|
||||
verilog-library-files)))
|
||||
|
||||
;;
|
||||
;; Module Information
|
||||
|
|
@ -10270,8 +10359,9 @@ When MODI is non-null, also add to modi-cache, for tracking."
|
|||
direction))
|
||||
indent-pt)
|
||||
(insert (if v2k "," ";"))
|
||||
(if (or (not (verilog-sig-comment sig))
|
||||
(equal "" (verilog-sig-comment sig)))
|
||||
(if (or (not verilog-auto-wire-comment)
|
||||
(not (verilog-sig-comment sig))
|
||||
(equal "" (verilog-sig-comment sig)))
|
||||
(insert "\n")
|
||||
(indent-to (max 48 (+ indent-pt 40)))
|
||||
(verilog-insert "// " (verilog-sig-comment sig) "\n"))
|
||||
|
|
@ -10821,9 +10911,9 @@ Ignores WHITESPACE if t, and writes output to stdout if SHOW."
|
|||
Differences are between buffers B1 and B2, starting at point
|
||||
DIFFPT. This function is called via `verilog-diff-function'."
|
||||
(let ((name1 (with-current-buffer b1 (buffer-file-name))))
|
||||
(verilog-warn "%s:%d: Difference in AUTO expansion found"
|
||||
name1 (with-current-buffer b1
|
||||
(count-lines (point-min) diffpt)))
|
||||
(verilog-warn-error "%s:%d: Difference in AUTO expansion found"
|
||||
name1 (with-current-buffer b1
|
||||
(count-lines (point-min) diffpt)))
|
||||
(cond (noninteractive
|
||||
(verilog-diff-file-with-buffer name1 b2 t t))
|
||||
(t
|
||||
|
|
@ -13040,7 +13130,7 @@ Typing \\[verilog-auto] will make this into:
|
|||
(verilog-read-signals
|
||||
(save-excursion
|
||||
(verilog-re-search-backward-quick
|
||||
"\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
|
||||
"\\(@\\|\\<\\(begin\\|if\\|case[xz]?\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
|
||||
(point))
|
||||
(point)))))
|
||||
(save-excursion
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue