Sync with upstream verilog-mode revision aa4b777
* lisp/progmodes/verilog-mode.el (verilog-mode-version): Update. (verilog-auto-end-comment-lines-re, verilog-end-block-ordered-re) (verilog-set-auto-endcomments): Automatically comment property/ endproperty blocks to match other similar blocks like sequence/ endsequence, function/endfunction, etc. Reported by Alex Reed. (verilog-set-auto-endcomments): Fix end comments for functions of type void, etc. Detect the function- or task-name when auto-commenting blocks that lack an explicit portlist. Reported by Alex Reed. (verilog-nameable-item-re): Fix nameable items that can have an end-identifier to include endchecker, endgroup, endprogram, endproperty, and endsequence. Reported by Alex Reed. (verilog-preprocessor-re, verilog-beg-of-statement): Fix indentation of property/endproperty around pre-processor directives. Reported by Alex Reed. (verilog-label-be): When auto-commenting a buffer, consider auto-comments on all known keywords (not just a subset thereof). Reported by Alex Reed. (verilog-beg-of-statement): Fix labeling do-while blocks, bug842. Reported by Alex Reed. (verilog-beg-of-statement-1, verilog-at-constraint-p): Fix hanging with many curly-bracket pairs, bug663. (verilog-do-indent): Fix electric tab deleting form-feeds. Note caused by indent-line-to deleting tabls pre 24.5. (verilog-auto-output, verilog-auto-input, verilog-auto-inout) (verilog-auto-inout-module, verilog-auto-inout-in): Doc fixes. (verilog-read-always-signals, verilog-auto-sense-sigs) (verilog-auto-reset): Fix AUTORESET with always_comb and always_latch, bug844. Reported by Greg Hilton. Author: Alex Reed <acreed4@gmail.com> (tiny change) * lisp/progmodes/verilog-mode.el (verilog-no-indent-begin-re): Fix `verilog-indent-begin-after-if' nil not honoring 'forever', 'foreach', and 'do' keywords. (verilog-endcomment-reason-re, verilog-beg-of-statement): Fix labeling do-while blocks, bug842. (verilog-backward-token): Fix indenting sensitivity lists with named events, bug840.
This commit is contained in:
Wilson Snyder
Glenn Morris
parent
fb0fcda820
commit
d282d6a595
2 changed files with 183 additions and 61 deletions
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@ -1,3 +1,46 @@
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2014-12-09 Wilson Snyder <wsnyder@wsnyder.org>
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Sync with upstream verilog-mode revision aa4b777.
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* progmodes/verilog-mode.el (verilog-mode-version): Update.
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(verilog-auto-end-comment-lines-re, verilog-end-block-ordered-re)
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(verilog-set-auto-endcomments): Automatically comment property/
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endproperty blocks to match other similar blocks like sequence/
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endsequence, function/endfunction, etc. Reported by Alex Reed.
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(verilog-set-auto-endcomments): Fix end comments for functions of
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type void, etc. Detect the function- or task-name when
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auto-commenting blocks that lack an explicit portlist.
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Reported by Alex Reed.
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(verilog-nameable-item-re): Fix nameable items that can have an
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end-identifier to include endchecker, endgroup, endprogram,
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endproperty, and endsequence. Reported by Alex Reed.
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(verilog-preprocessor-re, verilog-beg-of-statement):
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Fix indentation of property/endproperty around pre-processor
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directives. Reported by Alex Reed.
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(verilog-label-be): When auto-commenting a buffer, consider
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auto-comments on all known keywords (not just a subset thereof).
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Reported by Alex Reed.
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(verilog-beg-of-statement): Fix labeling do-while blocks, bug842.
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Reported by Alex Reed.
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(verilog-beg-of-statement-1, verilog-at-constraint-p):
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Fix hanging with many curly-bracket pairs, bug663.
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(verilog-do-indent): Fix electric tab deleting form-feeds.
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Note caused by indent-line-to deleting tabls pre 24.5.
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(verilog-auto-output, verilog-auto-input, verilog-auto-inout)
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(verilog-auto-inout-module, verilog-auto-inout-in): Doc fixes.
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(verilog-read-always-signals, verilog-auto-sense-sigs)
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(verilog-auto-reset): Fix AUTORESET with always_comb and always_latch,
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bug844. Reported by Greg Hilton.
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2014-12-09 Alex Reed <acreed4@gmail.com> (tiny change)
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* progmodes/verilog-mode.el (verilog-no-indent-begin-re):
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Fix `verilog-indent-begin-after-if' nil not honoring 'forever',
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'foreach', and 'do' keywords.
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(verilog-endcomment-reason-re, verilog-beg-of-statement):
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Fix labeling do-while blocks, bug842.
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(verilog-backward-token): Fix indenting sensitivity lists with
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named events, bug840.
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2014-12-09 Reto Zimmermann <reto@gnu.org>
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Sync with upstream vhdl mode v3.36.1.
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@ -123,7 +123,7 @@
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;;; Code:
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "2014-10-03-c075a49-vpo"
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(defconst verilog-mode-version "2014-11-12-aa4b777-vpo"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -2269,8 +2269,9 @@ find the errors."
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(defconst verilog-no-indent-begin-re
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(eval-when-compile
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(verilog-regexp-words
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'( "if" "else" "while" "for" "repeat" "always" "always_comb" "always_ff" "always_latch"
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"initial" "final"))))
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'("always" "always_comb" "always_ff" "always_latch" "initial" "final" ;; procedural blocks
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"if" "else" ;; conditional statements
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"while" "for" "foreach" "repeat" "do" "forever" )))) ;; loop statements
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(defconst verilog-ends-re
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;; Parenthesis indicate type of keyword found
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@ -2328,6 +2329,7 @@ find the errors."
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"endinterface"
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"endpackage"
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"endsequence"
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"endproperty"
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"endspecify"
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"endtable"
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"endtask"
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@ -2360,6 +2362,7 @@ find the errors."
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"\\(program\\)\\|" ; 13
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"\\(sequence\\)\\|" ; 14
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"\\(clocking\\)\\|" ; 15
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"\\(property\\)\\|" ; 16
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"\\)\\>\\)"))
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(defconst verilog-end-block-re
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(eval-when-compile
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@ -2424,7 +2427,7 @@ find the errors."
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"\\(\\<package\\>\\)\\|"
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"\\(\\<final\\>\\)\\|"
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"\\(@\\)\\|"
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"\\(\\<while\\>\\)\\|"
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"\\(\\<while\\>\\)\\|\\(\\<do\\>\\)\\|"
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"\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
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"\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
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"#"))
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@ -2518,15 +2521,20 @@ find the errors."
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"join" "join_any" "join_none"
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"end"
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"endcase"
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"endconfig"
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"endchecker"
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"endclass"
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"endclocking"
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"endconfig"
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"endfunction"
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"endgenerate"
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"endgroup"
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"endmodule"
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"endprimitive"
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"endinterface"
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"endpackage"
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"endprogram"
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"endproperty"
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"endsequence"
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"endspecify"
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"endtable"
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"endtask" )
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@ -2756,10 +2764,45 @@ find the errors."
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"String used to mark end of excluded text.")
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(defconst verilog-preprocessor-re
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(eval-when-compile
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(verilog-regexp-words
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`(
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"`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
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))))
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(concat
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;; single words
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"\\(?:"
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(verilog-regexp-words
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`("`__FILE__"
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"`__LINE__"
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"`celldefine"
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"`else"
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"`end_keywords"
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"`endcelldefine"
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"`endif"
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"`nounconnected_drive"
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"`resetall"
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"`unconnected_drive"
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"`undefineall"))
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"\\)\\|\\(?:"
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;; two words: i.e. `ifdef DEFINE
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"\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
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"\\)\\|\\(?:"
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;; `line number "filename" level
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"\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
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"\\)\\|\\(?:"
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;;`include "file" or `include <file>
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"\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
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"\\)\\|\\(?:"
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;; `pragma <stuff> (no mention in IEEE 1800-2012 that pragma can span multiple lines
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"\\<\\(`pragma\\)\\>\\s-+.+$"
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"\\)\\|\\(?:"
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;; `timescale time_unit / time_precision
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"\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
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"\\)\\|\\(?:"
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;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
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;; from http://www.emacswiki.org/emacs/MultilineRegexp
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(concat "\\<\\(`define\\|`if\\)\\>" ;; directive
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"\\s-+" ;; separator
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"\\(.*\\(?:\n.*\\)*?\\)" ;; definition: to tend of line, the maybe more lines (excludes any trailing \n)
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"\\(?:\n\\s-*\n\\|\\'\\)") ;; blank line or EOF
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"\\)"
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)))
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(defconst verilog-keywords
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'( "`case" "`default" "`define" "`else" "`endfor" "`endif"
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@ -4126,9 +4169,7 @@ Uses `verilog-scan' cache."
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(while (and
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(> (marker-position e) (point))
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(verilog-re-search-forward
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(concat
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"\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
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"\\|\\(`endif\\)\\|\\(`else\\)")
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verilog-auto-end-comment-lines-re
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nil 'move))
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(goto-char (match-beginning 0))
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(let ((indent-str (verilog-indent-line)))
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@ -4157,45 +4198,47 @@ Uses `verilog-scan' cache."
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;; or the token before us unambiguously ends a statement,
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;; then move back a token and test again.
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(not (or
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;; stop if beginning of buffer
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(bolp)
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;; stop if we find a ;
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;; stop if beginning of buffer
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(bobp)
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;; stop if we find a ;
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(= (preceding-char) ?\;)
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;; stop if we see a named coverpoint
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;; stop if we see a named coverpoint
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(looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
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;; keep going if we are in the middle of a word
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;; keep going if we are in the middle of a word
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(not (or (looking-at "\\<") (forward-word -1)))
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;; stop if we see an assertion (perhaps labeled)
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;; stop if we see an assertion (perhaps labeled)
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(and
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(looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
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(progn
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(setq h (point))
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(save-excursion
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(verilog-backward-token)
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(if (looking-at verilog-label-re)
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(setq h (point))))
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(goto-char h)))
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;; stop if we see an extended complete reg, perhaps a complete one
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(setq h (point))
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(save-excursion
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(verilog-backward-token)
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(if (looking-at verilog-label-re)
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(setq h (point))))
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(goto-char h)))
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;; stop if we see an extended complete reg, perhaps a complete one
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(and
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(looking-at verilog-complete-reg)
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(let* ((p (point)))
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(while (and (looking-at verilog-extended-complete-re)
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(progn (setq p (point))
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(verilog-backward-token)
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(/= p (point)))))
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(goto-char p)))
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;; stop if we see a complete reg (previous found extended ones)
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(looking-at verilog-complete-reg)
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(let* ((p (point)))
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(while (and (looking-at verilog-extended-complete-re)
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(progn (setq p (point))
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(verilog-backward-token)
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(/= p (point)))))
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(goto-char p)))
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;; stop if we see a complete reg (previous found extended ones)
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(looking-at verilog-basic-complete-re)
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;; stop if previous token is an ender
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;; stop if previous token is an ender
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(save-excursion
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(verilog-backward-token)
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(or
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(looking-at verilog-end-block-re)
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(looking-at verilog-preprocessor-re))))) ;; end of test
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(verilog-backward-syntactic-ws)
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(verilog-backward-token))
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(verilog-backward-token)
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(looking-at verilog-end-block-re))))
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(verilog-backward-syntactic-ws)
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(verilog-backward-token))
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;; Now point is where the previous line ended.
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(verilog-forward-syntactic-ws)))
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(verilog-forward-syntactic-ws)
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;; Skip forward over any preprocessor directives, as they have wacky indentation
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(if (looking-at verilog-preprocessor-re)
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(progn (goto-char (match-end 0))
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(verilog-forward-syntactic-ws)))))
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(defun verilog-beg-of-statement-1 ()
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"Move backward to beginning of statement."
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@ -4209,13 +4252,12 @@ Uses `verilog-scan' cache."
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(verilog-backward-syntactic-ws)
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(if (or (bolp)
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(= (preceding-char) ?\;)
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(save-excursion
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(progn
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(verilog-backward-token)
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(looking-at verilog-ends-re)))
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(progn
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(goto-char pt)
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(throw 'done t))
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(verilog-backward-token))))
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(throw 'done t)))))
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(verilog-forward-syntactic-ws)))
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;
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; (while (and
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@ -4773,10 +4815,10 @@ primitive or interface named NAME."
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(cond
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((match-end 5) ;; of verilog-end-block-ordered-re
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(setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
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(setq name-re "\\w+\\s-*("))
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(setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
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((match-end 6) ;; of verilog-end-block-ordered-re
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(setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
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(setq name-re "\\w+\\s-*("))
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(setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
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((match-end 7) ;; of verilog-end-block-ordered-re
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(setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
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((match-end 8) ;; of verilog-end-block-ordered-re
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@ -4795,6 +4837,8 @@ primitive or interface named NAME."
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(setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
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((match-end 15) ;; of verilog-end-block-ordered-re
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(setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
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((match-end 16) ;; of verilog-end-block-ordered-re
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(setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
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(t (error "Problem in verilog-set-auto-endcomments")))
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(let (b e)
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@ -5849,7 +5893,9 @@ Set point to where line starts."
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(;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
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t
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(forward-word -1)
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(while (= (preceding-char) ?\_)
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(while (or (= (preceding-char) ?\_)
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(= (preceding-char) ?\@)
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(= (preceding-char) ?\.))
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(forward-word -1))
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(cond
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((looking-at "\\<else\\>")
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|
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@ -6103,14 +6149,18 @@ Return >0 for nested struct."
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(defun verilog-at-constraint-p ()
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"If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
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(if (save-excursion
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(let ((p (point)))
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(and
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(equal (char-after) ?\{)
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(forward-list)
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(progn (backward-char 1)
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(verilog-backward-ws&directives)
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(and
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(or (equal (char-before) ?\{) ;; empty case
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(equal (char-before) ?\;)
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(equal (char-before) ?\})))))
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(equal (char-before) ?\}))
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;; skip what looks like bus repitition operator {#{
|
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(not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
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(progn
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(let ( (pt (point)) (pass 0))
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(verilog-backward-ws&directives)
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|
|
@ -6429,6 +6479,9 @@ Only look at a few lines to determine indent level."
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(looking-at verilog-declaration-re))
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(verilog-indent-declaration ind))
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|
||||
(;-- form feeds - ignored as bug in indent-line-to in < 24.5
|
||||
(looking-at "\f"))
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||||
|
||||
(;-- Everything else
|
||||
t
|
||||
(let ((val (eval (cdr (assoc type verilog-indent-alist)))))
|
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|
|
@ -8894,7 +8947,6 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
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(save-excursion
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(let* (;;(dbg "")
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sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
|
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(search-forward ")")
|
||||
(verilog-read-always-signals-recurse nil nil nil)
|
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(setq sigs-out-i (append sigs-out-i sigs-out-unk)
|
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sigs-out-unk nil)
|
||||
|
|
@ -11731,6 +11783,9 @@ Limitations:
|
|||
|
||||
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
||||
|
||||
Types are added to declarations if an AUTOLOGIC or
|
||||
`verilog-auto-wire-type' is set to logic.
|
||||
|
||||
Signals matching `verilog-auto-output-ignore-regexp' are not included.
|
||||
|
||||
An example (see `verilog-auto-inst' for what else is going on here):
|
||||
|
|
@ -11872,6 +11927,9 @@ Limitations:
|
|||
|
||||
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
||||
|
||||
Types are added to declarations if an AUTOLOGIC or
|
||||
`verilog-auto-wire-type' is set to logic.
|
||||
|
||||
Signals matching `verilog-auto-input-ignore-regexp' are not included.
|
||||
|
||||
An example (see `verilog-auto-inst' for what else is going on here):
|
||||
|
|
@ -11952,6 +12010,9 @@ Limitations:
|
|||
|
||||
Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
||||
|
||||
Types are added to declarations if an AUTOLOGIC or
|
||||
`verilog-auto-wire-type' is set to logic.
|
||||
|
||||
Signals matching `verilog-auto-inout-ignore-regexp' are not included.
|
||||
|
||||
An example (see `verilog-auto-inst' for what else is going on here):
|
||||
|
|
@ -12068,13 +12129,14 @@ same expansion will result from only extracting signals starting with i:
|
|||
|
||||
/*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
|
||||
|
||||
You may also provide an optional second regular expression, in
|
||||
which case only signals which have that pin direction and data
|
||||
type will be included. This matches against everything before
|
||||
the signal name in the declaration, for example against
|
||||
\"input\" (single bit), \"output logic\" (direction and type) or
|
||||
\"output [1:0]\" (direction and implicit type). You also
|
||||
probably want to skip spaces in your regexp.
|
||||
You may also provide an optional third argument regular
|
||||
expression, in which case only signals which have that pin
|
||||
direction and data type matching that regular expression will be
|
||||
included. This matches against everything before the signal name
|
||||
in the declaration, for example against \"input\" (single bit),
|
||||
\"output logic\" (direction and type) or \"output
|
||||
[1:0]\" (direction and implicit type). You also probably want to
|
||||
skip spaces in your regexp.
|
||||
|
||||
For example, the below will result in matching the output \"o\"
|
||||
against the previous example's module:
|
||||
|
|
@ -12193,7 +12255,21 @@ You may also provide an optional regular expression, in which case only
|
|||
signals matching the regular expression will be included. For example the
|
||||
same expansion will result from only extracting signals starting with i:
|
||||
|
||||
/*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
|
||||
/*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
|
||||
|
||||
You may also provide an optional third argument regular
|
||||
expression, in which case only signals which have that pin
|
||||
direction and data type matching that regular expression will be
|
||||
included. This matches against everything before the signal name
|
||||
in the declaration, for example against \"input\" (single bit),
|
||||
\"output logic\" (direction and type) or \"output
|
||||
[1:0]\" (direction and implicit type). You also probably want to
|
||||
skip spaces in your regexp.
|
||||
|
||||
For example, the below will result in matching the output \"o\"
|
||||
against the previous example's module:
|
||||
|
||||
/*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/"
|
||||
(verilog-auto-inout-module t nil))
|
||||
|
||||
(defun verilog-auto-inout-in ()
|
||||
|
|
@ -12244,7 +12320,7 @@ You may also provide an optional regular expression, in which case only
|
|||
signals matching the regular expression will be included. For example the
|
||||
same expansion will result from only extracting signals starting with i:
|
||||
|
||||
/*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
|
||||
/*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
|
||||
(verilog-auto-inout-module nil t))
|
||||
|
||||
(defun verilog-auto-inout-param ()
|
||||
|
|
@ -12516,7 +12592,9 @@ See `verilog-auto-insert-lisp' for examples."
|
|||
|
||||
(defun verilog-auto-sense-sigs (moddecls presense-sigs)
|
||||
"Return list of signals for current AUTOSENSE block."
|
||||
(let* ((sigss (verilog-read-always-signals))
|
||||
(let* ((sigss (save-excursion
|
||||
(search-forward ")")
|
||||
(verilog-read-always-signals)))
|
||||
(sig-list (verilog-signals-not-params
|
||||
(verilog-signals-not-in (verilog-alw-get-inputs sigss)
|
||||
(append (and (not verilog-auto-sense-include-inputs)
|
||||
|
|
@ -12706,11 +12784,12 @@ Typing \\[verilog-auto] will make this into:
|
|||
(save-excursion
|
||||
(verilog-read-signals
|
||||
(save-excursion
|
||||
(verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
|
||||
(verilog-re-search-backward-quick
|
||||
"\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
|
||||
(point))
|
||||
(point)))))
|
||||
(save-excursion
|
||||
(verilog-re-search-backward-quick "@" nil t)
|
||||
(verilog-re-search-backward-quick "\\(@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
|
||||
(setq sigss (verilog-read-always-signals)))
|
||||
(setq dly-list (verilog-alw-get-outputs-delayed sigss))
|
||||
(setq sig-list (verilog-signals-not-in (append
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue