verilog-mode.el: Fix AUTOWIRE etc. range simplification with subtraction of negative number.
* lisp/progmodes/verilog-mode.el (verilog-simplify-range-expression): Fix AUTOWIRE etc. range simplification with subtraction of negative number (#1879).
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@ -9,7 +9,7 @@
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;; Keywords: languages
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;; The "Version" is the date followed by the decimal rendition of the Git
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;; commit hex.
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;; Version: 2024.03.01.121933719
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;; Version: 2024.10.09.140346409
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;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
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;; file on 19/3/2008, and the maintainer agreed that when a bug is
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@ -124,7 +124,7 @@
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;;
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "2024-03-01-7448f97-vpo-GNU"
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(defconst verilog-mode-version "2024-10-09-85d8429-vpo-GNU"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -11441,6 +11441,7 @@ This repairs those mis-inserted by an AUTOARG."
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;; Prefix regexp needs beginning of match, or some symbol of
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;; lesser or equal precedence. We assume the [:]'s exist in expr.
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;; Ditto the end.
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;;(message "sre: out=%s" out)
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(while (string-match
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(concat "\\([[({:*/<>+-]\\)" ; - must be last
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"(\\<\\([0-9A-Za-z_]+\\))"
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@ -11486,19 +11487,23 @@ This repairs those mis-inserted by an AUTOARG."
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out)
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(let ((pre (match-string 1 out))
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(lhs (string-to-number (match-string 2 out)))
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(op (match-string 3 out))
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(rhs (string-to-number (match-string 4 out)))
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(post (match-string 5 out))
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val)
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(when (equal pre "-")
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(setq lhs (- lhs)))
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(setq val (if (equal (match-string 3 out) "-")
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(setq val (if (equal op "-")
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(- lhs rhs)
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(+ lhs rhs))
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out (replace-match
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(concat (if (and (equal pre "-")
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(< val 0))
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"" ; Not "--20" but just "-20"
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pre)
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(concat (cond ((and (equal pre "-")
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(< val 0))
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"") ; Not "--20" but just "-20"
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((and (equal pre "-")
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(> val 0))
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"+") ; Not "-+20" but just "+20"
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(t pre))
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(int-to-string val)
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post)
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nil nil out)) ))
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@ -11526,19 +11531,20 @@ This repairs those mis-inserted by an AUTOARG."
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nil nil out)))))
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out)))
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;;(verilog-simplify-range-expression "[1:3]") ; 1
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;;(verilog-simplify-range-expression "[(1):3]") ; 1
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;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ; 20
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;;(verilog-simplify-range-expression "[(2*3+6*7)]") ; 48
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;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ; FOO*4-2
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;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ; FOO*4+0
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;;(verilog-simplify-range-expression "[(func(BAR))]") ; func(BAR)
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;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; FOO-0
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;;(verilog-simplify-range-expression "[$clog2(2)]") ; 1
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;;(verilog-simplify-range-expression "[$clog2(7)]") ; 3
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;;(verilog-simplify-range-expression "[(TEST[1])-1:0]")
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;;(verilog-simplify-range-expression "[1<<2:8>>2]") ; [4:2]
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;;(verilog-simplify-range-expression "[2*4/(4-2) +2+4 <<4 >>2]")
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;;(verilog-simplify-range-expression "[1:3]") ; "[1:3]"
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;;(verilog-simplify-range-expression "[(1):3]") ; "[1:3]"
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;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ; "[20]"
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;;(verilog-simplify-range-expression "[(2*3+6*7)]") ; "[48]"
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;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ; "[FOO*4-2]"
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;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ; "[FOO*4+0]"
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;;(verilog-simplify-range-expression "[(func(BAR))]") ; "[func(BAR)]"
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;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; "[FOO-0]"
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;;(verilog-simplify-range-expression "[FOO-1+2:LSB-3+1]") ; "[FOO+1:LSB-1]"
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;;(verilog-simplify-range-expression "[$clog2(2)]") ; "[1]"
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;;(verilog-simplify-range-expression "[$clog2(7)]") ; "[3]"
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;;(verilog-simplify-range-expression "[(TEST[1])-1:0]") ; "[(TEST[1])-1:0]"
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;;(verilog-simplify-range-expression "[1<<2:8>>2]") ; "[4:2]"
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;;(verilog-simplify-range-expression "[2*4/(4-2) +2+4 <<4 >>2]") ; "[8/(2) +2+4 <<4 >>2]"
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;;(verilog-simplify-range-expression "[WIDTH*2/8-1:0]") ; "[WIDTH*2/8-1:0]"
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;;(verilog-simplify-range-expression "[(FOO).size:0]") ; "[FOO.size:0]"
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