Verilog-mode update from upstream https://github.com/veripool/verilog-mode
* lisp/progmodes/verilog-mode.el (verilog-auto-inst) (verilog-auto-inst-param): Remove intended formfeeds. Our ability to detect unintended formfeeds elsewhere outweighs their limited utility here. Contributed by Mattias Engdegård. (verilog-at-constraint-p) (verilog-at-struct-mv-p, verilog-at-struct-p, verilog-calc-1) (verilog-in-case-region-p, verilog-in-fork-region-p) (verilog-in-generate-region-p, verilog-set-auto-endcomments): Fix indentation problem when there is a signal named "module_something" (#1861). Cleanup RexEx groupings. (verilog-read-sub-decls-expr): Fix apostrophe parser in AUTOWIRE (#1854) (#1855). (verilog-auto-inst-port): Fix AUTOINST multi-dimensional array [] substitution. Reported by Caleb Begly. (verilog-property-re, verilog-beg-of-statement, verilog-calc-1): Concurrent SVA statement pattern-matching learns 'restrict property' and 'cover sequence' expression for proper indentation around those constructs. This addresses more patterns in IEEE 1800-2017's 'concurrent_sasertion_statement' grammar. (verilog-read-sub-decls-line): Fix `verilog-auto-ignore-concat' with parenthesis signals. Reported by Dmitri Sorkin. (verilog-simplify-range-expression): Fix `verilog-auto-inst-param-value' confusing structure selects. Reported by Mike Bertone.
This commit is contained in:
Wilson Snyder
parent
31a4bec609
commit
b2d18ff944
1 changed files with 69 additions and 45 deletions
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@ -9,7 +9,7 @@
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;; Keywords: languages
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;; The "Version" is the date followed by the decimal rendition of the Git
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;; commit hex.
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;; Version: 2023.06.06.141322628
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;; Version: 2024.03.01.121933719
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;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
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;; file on 19/3/2008, and the maintainer agreed that when a bug is
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@ -124,7 +124,7 @@
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;;
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "2023-06-06-86c6984-vpo-GNU"
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(defconst verilog-mode-version "2024-03-01-7448f97-vpo-GNU"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -2556,11 +2556,13 @@ find the errors."
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(defconst verilog-assignment-operation-re-2
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(concat "\\(.*?\\)" verilog-assignment-operator-re))
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;; Loosely related to IEEE 1800's concurrent_assertion_statement
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(defconst verilog-concurrent-assertion-statement-re
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"\\(\\<\\(assert\\|assume\\|cover\\|restrict\\)\\>\\s-+\\<\\(property\\|sequence\\)\\>\\)\\|\\(\\<assert\\>\\)")
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(defconst verilog-label-re (concat verilog-identifier-sym-re "\\s-*:\\s-*"))
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(defconst verilog-property-re
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(concat "\\(" verilog-label-re "\\)?"
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;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
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"\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
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(concat "\\(" verilog-label-re "\\)?" verilog-concurrent-assertion-statement-re))
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(defconst verilog-no-indent-begin-re
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(eval-when-compile
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@ -2715,7 +2717,6 @@ find the errors."
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"\\(\\<fork\\>\\)\\|" ; 7
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"\\(\\<if\\>\\)\\|"
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verilog-property-re "\\|"
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"\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
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"\\(\\<clocking\\>\\)\\|"
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"\\(\\<task\\>\\)\\|"
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"\\(\\<function\\>\\)\\|"
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@ -4843,7 +4844,7 @@ Uses `verilog-scan' cache."
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(not (or (looking-at "\\<") (forward-word-strictly -1)))
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;; stop if we see an assertion (perhaps labeled)
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(and
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(looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
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(looking-at (concat "\\(\\w+\\W*:\\W*\\)?" verilog-concurrent-assertion-statement-re))
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(progn
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(setq h (point))
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(save-excursion
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@ -4970,7 +4971,7 @@ More specifically, point @ in the line foo : @ begin"
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(while t
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(verilog-re-search-backward
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(concat "\\(\\<module\\>\\)\\|\\(\\<connectmodule\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
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"\\(\\<endcase\\>\\)\\>")
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"\\(\\<endcase\\>\\)")
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nil 'move)
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(cond
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((match-end 4)
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@ -5010,7 +5011,7 @@ More specifically, after a generate and before an endgenerate."
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(while (and
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(/= nest 0)
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(verilog-re-search-backward
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"\\<\\(module\\)\\|\\(connectmodule\\)\\|\\(endmodule\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\|\\(if\\)\\|\\(case\\)\\|\\(for\\)\\>" nil 'move)
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"\\<\\(?:\\(module\\)\\|\\(connectmodule\\)\\|\\(endmodule\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\|\\(if\\)\\|\\(case\\)\\|\\(for\\)\\)\\>" nil 'move)
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(cond
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((match-end 1) ; module - we have crawled out
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(throw 'done 1))
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@ -5038,7 +5039,7 @@ More specifically, after a generate and before an endgenerate."
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(save-excursion
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(while (and
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(/= nest 0)
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(verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
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(verilog-re-search-backward "\\<\\(?:\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\)\\>" lim 'move)
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(cond
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((match-end 1) ; fork
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(setq nest (1- nest)))
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@ -5335,7 +5336,7 @@ primitive or interface named NAME."
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(match-end 3)
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(goto-char there)
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(let ((nest 0)
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(reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
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(reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(\\<assert\\>\\)"))
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(catch 'skip
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(while (verilog-re-search-backward reg nil 'move)
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(cond
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@ -6244,7 +6245,7 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
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(match-end 22))
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(throw 'continue 'foo))
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((looking-at "\\<class\\|struct\\|function\\|task\\>")
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((looking-at "\\<\\(?:class\\|struct\\|function\\|task\\)\\>")
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;; *sigh* These words have an optional prefix:
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;; extern {virtual|protected}? function a();
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;; and we don't want to confuse this with
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@ -6268,12 +6269,16 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
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(throw 'nesting 'defun))))
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;;
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((looking-at "\\<property\\>")
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((looking-at "\\<\\(property\\|sequence\\)\\>")
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;; *sigh*
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;; {assert|assume|cover} property (); are complete
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;; and could also be labeled: - foo: assert property
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;; but
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;; property ID () ... needs endproperty
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;; - {assert|assume|cover|restrict} property (); are complete
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;; - cover sequence (); is complete
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;; and could also be labeled:
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;; - foo: assert property
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;; - bar: cover sequence
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;; but:
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;; - property ID () ... needs endproperty
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;; - sequence ID () ... needs endsequence
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(verilog-beg-of-statement)
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(if (looking-at verilog-property-re)
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(throw 'continue 'statement) ; We don't need an endproperty for these
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@ -6940,7 +6945,7 @@ Also move point to constraint."
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(let ( (pt (point)) (pass 0))
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(verilog-backward-ws&directives)
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(verilog-backward-token)
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(if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
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(if (looking-at (concat "\\<\\(?:constraint\\|coverpoint\\|cross\\|with\\)\\>\\|" verilog-in-constraint-re))
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(progn (setq pass 1)
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(if (looking-at "\\<with\\>")
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(progn (verilog-backward-ws&directives)
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@ -6981,7 +6986,7 @@ Also move point to constraint."
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(save-excursion
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(if (and (equal (char-after) ?\{)
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(verilog-backward-token))
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(looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
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(looking-at "\\<\\(?:struct\\|union\\|packed\\|\\(un\\)?signed\\)\\>")
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nil)))
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(defun verilog-at-struct-mv-p ()
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@ -6989,7 +6994,7 @@ Also move point to constraint."
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(let ((pt (point)))
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(if (and (equal (char-after) ?\{)
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(verilog-backward-token))
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(if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
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(if (looking-at "\\<\\(?:struct\\|union\\|packed\\|\\(un\\)?signed\\)\\>")
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(progn (verilog-beg-of-statement) (point))
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(progn (goto-char pt) nil))
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(progn (goto-char pt) nil))))
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@ -9675,7 +9680,7 @@ Return an array of [outputs inouts inputs wire reg assign const gparam intf]."
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(cond
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;; {..., a, b} requires us to recurse on a,b
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;; To support {#{},{#{a,b}} we'll just split everything on [{},]
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((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
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((string-match "^\\s-*'?{\\(.*\\)}\\s-*$" expr)
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(let ((mlst (split-string (match-string 1 expr) "[{},]"))
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mstr)
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(while (setq mstr (pop mlst))
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@ -9755,7 +9760,10 @@ Inserts the list of signals found, using submodi to look up each port."
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;; We intentionally ignore (non-escaped) signals with .s in them
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;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
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(when port
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(cond ((looking-at "[^\n]*AUTONOHOOKUP"))
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(cond ((and verilog-auto-ignore-concat
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(looking-at "[({]"))
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nil) ; {...} or (...) historically ignored with auto-ignore-concat
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((looking-at "[^\n]*AUTONOHOOKUP"))
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((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
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(verilog-read-sub-decls-sig
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submoddecls par-values comment port
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@ -11436,7 +11444,7 @@ This repairs those mis-inserted by an AUTOARG."
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(while (string-match
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(concat "\\([[({:*/<>+-]\\)" ; - must be last
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"(\\<\\([0-9A-Za-z_]+\\))"
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"\\([])}:*/<>+-]\\)")
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"\\([])}:*/<>.+-]\\)")
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out)
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(setq out (replace-match "\\1\\2\\3" nil nil out)))
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(while (string-match
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@ -11531,7 +11539,8 @@ This repairs those mis-inserted by an AUTOARG."
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;;(verilog-simplify-range-expression "[(TEST[1])-1:0]")
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;;(verilog-simplify-range-expression "[1<<2:8>>2]") ; [4:2]
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;;(verilog-simplify-range-expression "[2*4/(4-2) +2+4 <<4 >>2]")
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;;(verilog-simplify-range-expression "[WIDTH*2/8-1:0]")
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;;(verilog-simplify-range-expression "[WIDTH*2/8-1:0]") ; "[WIDTH*2/8-1:0]"
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;;(verilog-simplify-range-expression "[(FOO).size:0]") ; "[FOO.size:0]"
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(defun verilog-clog2 (value)
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"Compute $clog2 - ceiling log2 of VALUE."
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@ -12247,18 +12256,12 @@ If PAR-VALUES replace final strings with these parameter values."
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(vl-memory (verilog-sig-memory port-st))
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(vl-mbits (if (verilog-sig-multidim port-st)
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(verilog-sig-multidim-string port-st) ""))
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(vl-bits (if (or (eq verilog-auto-inst-vector t)
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(and (eq verilog-auto-inst-vector `unsigned)
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(not (verilog-sig-signed port-st)))
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(not (assoc port (verilog-decls-get-signals moddecls)))
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(not (equal (verilog-sig-bits port-st)
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(verilog-sig-bits
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(assoc port (verilog-decls-get-signals moddecls))))))
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(or (verilog-sig-bits port-st) "")
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""))
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(vl-bits (or (verilog-sig-bits port-st) ""))
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(case-fold-search nil)
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(check-values par-values)
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tpl-net dflt-bits)
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auto-inst-vector
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auto-inst-vector-tpl
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tpl-net dflt-bits)
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;; Replace parameters in bit-width
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(when (and check-values
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(not (equal vl-bits "")))
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@ -12281,6 +12284,16 @@ If PAR-VALUES replace final strings with these parameter values."
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vl-mbits (verilog-simplify-range-expression vl-mbits)
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vl-memory (when vl-memory (verilog-simplify-range-expression vl-memory))
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vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
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(setq auto-inst-vector
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(if (or (eq verilog-auto-inst-vector t)
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(and (eq verilog-auto-inst-vector `unsigned)
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(not (verilog-sig-signed port-st)))
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(not (assoc port (verilog-decls-get-signals moddecls)))
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(not (equal (verilog-sig-bits port-st)
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(verilog-sig-bits
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(assoc port (verilog-decls-get-signals moddecls))))))
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vl-bits
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""))
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;; Default net value if not found
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(setq dflt-bits (if (or (and (verilog-sig-bits port-st)
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(verilog-sig-multidim port-st))
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@ -12290,7 +12303,7 @@ If PAR-VALUES replace final strings with these parameter values."
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(if vl-memory "." "")
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(if vl-memory vl-memory "")
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"*/")
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(concat vl-bits))
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(concat auto-inst-vector))
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tpl-net (concat port
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(if (and vl-modport
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;; .modport cannot be added if attachment is
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@ -12329,10 +12342,21 @@ If PAR-VALUES replace final strings with these parameter values."
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(if (numberp value) (setq value (number-to-string value)))
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value))
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(substring tpl-net (match-end 0))))))
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;; Get range based off template net
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(setq auto-inst-vector-tpl
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(if (or (eq verilog-auto-inst-vector t)
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(and (eq verilog-auto-inst-vector `unsigned)
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(not (verilog-sig-signed port-st)))
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(not (assoc tpl-net (verilog-decls-get-signals moddecls)))
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(not (equal (verilog-sig-bits port-st)
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(verilog-sig-bits
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(assoc tpl-net (verilog-decls-get-signals moddecls))))))
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vl-bits
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""))
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;; Replace @ and [] magic variables in final output
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(setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
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(setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
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(setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
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(setq tpl-net (verilog-string-replace-matches "\\[\\]" auto-inst-vector-tpl nil nil tpl-net)))
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;; Insert it
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(when (or tpl-ass (not verilog-auto-inst-template-required))
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(verilog--auto-inst-first indent-pt section)
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@ -12502,7 +12526,7 @@ Typing \\[verilog-auto] will make this into:
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endmodule
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Where the list of inputs and outputs came from the inst module.
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Exceptions:
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Unless you are instantiating a module multiple times, or the module is
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@ -12527,7 +12551,7 @@ Exceptions:
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// Outputs
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.o (o[31:0]));
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Templates:
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For multiple instantiations based upon a single template, create a
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@ -12598,7 +12622,7 @@ Templates:
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.ptl_bus (ptl_busnew[3:0]),
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....
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Multiple Module Templates:
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The same template lines can be applied to multiple modules with
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@ -12613,7 +12637,7 @@ Multiple Module Templates:
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*/
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Note there is only one AUTO_TEMPLATE opening parenthesis.
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@ Templates:
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It is common to instantiate a cell multiple times, so templates make it
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@ -12678,7 +12702,7 @@ Multiple Module Templates:
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.ptl_mapvalidx (BAR_ptl_mapvalid),
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.ptl_mapvalidp1x (ptl_mapvalid_BAR));
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Regexp Templates:
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A template entry of the form
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@ -12702,7 +12726,7 @@ Regexp Templates:
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subscript:
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.\\(.*\\)_l (\\1_[]),
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Lisp Templates:
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First any regular expression template is expanded.
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@ -12747,7 +12771,7 @@ Lisp Templates:
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After the evaluation is completed, @ substitution and [] substitution
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occur.
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Ignoring Hookup:
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AUTOWIRE and related AUTOs will read the signals created by a template.
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@ -12756,7 +12780,7 @@ Ignoring Hookup:
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.pci_req_l (pci_req_not_to_wire), //AUTONOHOOKUP
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For more information see the \\[verilog-faq] and forums at URL
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`https://www.veripool.org'."
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(save-excursion
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@ -12910,7 +12934,7 @@ Typing \\[verilog-auto] will make this into:
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endmodule
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Where the list of parameter connections come from the inst module.
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Templates:
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|
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You can customize the parameter connections using AUTO_TEMPLATEs,
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|
|
|
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