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* verilog-mode.el (verilog-vmm-begin-re, verilog-vmm-end-re,

Browse source 
verilog-vmm-statement-re, verilog-ovm-statement-re,
verilog-defun-level-not-generate-re, verilog-calculate-indent,
verilog-leap-to-head, verilog-backward-token): Fix
indenting VMM macros.  Reported by Jonathan Ashbrook.

* verilog-mode.el (verilog-auto-lineup, verilog-nameable-item-re):
Cleanup user-visible spelling and documentation errors.  One
reported by Gary Delp.
(verilog-submit-bug-report): Mention bug tracking and CC
co-author.
(verilog-read-decls): Fix AUTOWIRE with types declared in a
package, bug195.  Reported by Pierre-David Pfister.
This commit is contained in:
Dan Nicolaescu 2009-12-11 02:31:49 +00:00
parent 47641aacc1
commit 86a4c7ac2b
2 changed files with 144 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

163
lisp/progmodes/verilog-mode.el
View file

@ -118,9 +118,9 @@
;;; Code:
;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "552"
(defconst verilog-mode-version "556"
"Version of this Verilog mode.")
(defconst verilog-mode-release-date "2009-11-25-GNU"
(defconst verilog-mode-release-date "2009-12-10-GNU"
"Release date of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
@ -426,7 +426,7 @@ are lineup only when \\[verilog-pretty-declarations] is typed."
:type '(radio (const :tag "Line up Assignments and Declarations" all)
(const :tag "Line up Assignment statements" assignments )
(const :tag "Line up Declarartions" declarations)
(const :tag "Line up Declarations" declarations)
(function :tag "Other"))
:group 'verilog-mode-indent )
@ -1203,7 +1203,7 @@ If set will become buffer local.")
:help "Help on AUTOARG - declaring module port list"]
["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
:help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-complement)
["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
:help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
:help "Help on AUTOINOUTMODULE - copying i/o from another file"]
@ -1553,6 +1553,38 @@ find the errors."
"`ovm_sequencer_utils_end"
) nil )))
(defconst verilog-vmm-begin-re
(eval-when-compile
(verilog-regexp-opt
'(
"`vmm_data_member_begin"
"`vmm_env_member_begin"
"`vmm_scenario_member_begin"
"`vmm_subenv_member_begin"
"`vmm_xactor_member_begin"
) nil ) ) )
(defconst verilog-vmm-end-re
(eval-when-compile
(verilog-regexp-opt
'(
"`vmm_data_member_end"
"`vmm_env_member_end"
"`vmm_scenario_member_end"
"`vmm_subenv_member_end"
"`vmm_xactor_member_end"
) nil ) ) )
(defconst verilog-vmm-statement-re
(eval-when-compile
(verilog-regexp-opt
'(
;; "`vmm_xactor_member_enum_array"
"`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
;; "`vmm_xactor_member_scalar_array"
;; "`vmm_xactor_member_scalar"
) nil )))
(defconst verilog-ovm-statement-re
(eval-when-compile
(verilog-regexp-opt
@ -1679,7 +1711,8 @@ find the errors."
(concat
"\\(\\<else\\>\\)\\|" ; 1
"\\(\\<if\\>\\)\\|" ; 2
"\\(\\<end\\>\\)\\|" ; 3
"\\(\\<assert\\>\\)\\|" ; 3
"\\(\\<end\\>\\)\\|" ; 3.1
"\\(\\<endcase\\>\\)\\|" ; 4
"\\(\\<endfunction\\>\\)\\|" ; 5
"\\(\\<endtask\\>\\)\\|" ; 6
@ -1689,6 +1722,12 @@ find the errors."
"\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
"\\(\\<endclass\\>\\)\\|" ; 11
"\\(\\<endgroup\\>\\)\\|" ; 12
;; VMM
"\\(\\<`vmm_data_member_end\\>\\)\\|"
"\\(\\<`vmm_env_member_end\\>\\)\\|"
"\\(\\<`vmm_scenario_member_end\\>\\)\\|"
"\\(\\<`vmm_subenv_member_end\\>\\)\\|"
"\\(\\<`vmm_xactor_member_end\\>\\)\\|"
;; OVM
"\\(\\<`ovm_component_utils_end\\>\\)\\|"
"\\(\\<`ovm_field_utils_end\\>\\)\\|"
@ -1777,7 +1816,12 @@ find the errors."
"`ovm_object_utils_end"
"`ovm_sequence_utils_end"
"`ovm_sequencer_utils_end"
;; VMM
"`vmm_data_member_end"
"`vmm_env_member_end"
"`vmm_scenario_member_end"
"`vmm_subenv_member_end"
"`vmm_xactor_member_end"
))))
@ -1832,7 +1876,12 @@ find the errors."
"`ovm_object_param_utils_begin"
"`ovm_sequence_utils_begin"
"`ovm_sequencer_utils_begin"
;; VMM
"`vmm_data_member_begin"
"`vmm_env_member_begin"
"`vmm_scenario_member_begin"
"`vmm_subenv_member_begin"
"`vmm_xactor_member_begin"
))))
;; These are the same words, in a specific order in the regular
;; expression so that matching will work nicely for
@ -1854,6 +1903,7 @@ find the errors."
"\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
"\\|\\(\\<clocking\\>\\)" ;22 27
"\\|\\(\\<`ovm_[a-z_]+_begin\\>\\)" ;28
"\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
;;
))
@ -1888,7 +1938,7 @@ find the errors."
"endfunction"
"endgenerate"
"endmodule"
"endprimative"
"endprimitive"
"endinterface"
"endpackage"
"endspecify"
@ -2025,6 +2075,18 @@ find the errors."
"`ovm_object_utils_end"
"`ovm_sequence_utils_end"
"`ovm_sequencer_utils_end"
;; VMM Begin tokens
"`vmm_data_member_begin"
"`vmm_env_member_begin"
"`vmm_scenario_member_begin"
"`vmm_subenv_member_begin"
"`vmm_xactor_member_begin"
;; VMM End tokens
"`vmm_data_member_end"
"`vmm_env_member_end"
"`vmm_scenario_member_end"
"`vmm_subenv_member_end"
"`vmm_xactor_member_end"
))))
(defconst verilog-defun-level-not-generate-re
@ -3251,7 +3313,7 @@ With ARG, first kill any existing labels."
(while
;; If the current point does not begin a new
;; statement, as in the character ahead of us is a ';', or SOF
;; or the string after us unambiguosly starts a statement,
;; or the string after us unambiguously starts a statement,
;; or the token before us unambiguously ends a statement,
;; then move back a token and test again.
(not (or
@ -4278,7 +4340,8 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
;; if we have a directive, done.
(if (save-excursion (beginning-of-line)
(and (looking-at verilog-directive-re-1)
(not (looking-at "[ \t]*`ovm_"))))
(not (or (looking-at "[ \t]*`ovm_")
(looking-at "[ \t]*`vmm_")))))
(throw 'nesting 'directive))
;; indent structs as if there were module level
(if (verilog-in-struct-p)
@ -4338,6 +4401,14 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
(beginning-of-line)
(verilog-forward-syntactic-ws)
(throw 'nesting 'statement)))))
((match-end 3) ; assert block
(setq elsec (1- elsec))
(verilog-beg-of-statement) ;; doesn't get to beginning
(if (looking-at (concat "\\(" verilog-label-re "\\)?"
"\\(assert\\|assume\\|cover\\)\\s-+property\\>"))
(throw 'nesting 'statement) ; We don't need an endproperty for these
(throw 'nesting 'block) ;We still need a endproperty
))
(t ; endblock
; try to leap back to matching outward block by striding across
; indent level changing tokens then immediately
@ -4345,34 +4416,34 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
(let (( reg) (nest 1))
;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
(cond
((match-end 3) ; end
((match-end 4) ; end
;; Search back for matching begin
(setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
((match-end 4) ; endcase
((match-end 5) ; endcase
;; Search back for matching case
(setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
((match-end 5) ; endfunction
((match-end 6) ; endfunction
;; Search back for matching function
(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
((match-end 6) ; endtask
((match-end 7) ; endtask
;; Search back for matching task
(setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
((match-end 7) ; endspecify
((match-end 8) ; endspecify
;; Search back for matching specify
(setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
((match-end 8) ; endtable
((match-end 9) ; endtable
;; Search back for matching table
(setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
((match-end 9) ; endgenerate
((match-end 10) ; endgenerate
;; Search back for matching generate
(setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
((match-end 10) ; joins
((match-end 11) ; joins
;; Search back for matching fork
(setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
((match-end 11) ; class
((match-end 12) ; class
;; Search back for matching class
(setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
((match-end 12) ; covergroup
((match-end 13) ; covergroup
;; Search back for matching covergroup
(setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
(catch 'skip
@ -4442,7 +4513,7 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
((equal (char-after) ?\})
(let ((there (verilog-at-close-constraint-p)))
(if there ;; we are at the } that closes a constraing. Find the { that opens it
(if there ;; we are at the } that closes a constraint. Find the { that opens it
(progn
(forward-char 1)
(backward-list 1)
@ -4624,6 +4695,9 @@ Jump from end to matching begin, from endcase to matching case, and so on."
((looking-at verilog-ovm-end-re)
;; 12: Search back for matching sequence
(setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
((looking-at verilog-vmm-end-re)
;; 12: Search back for matching sequence
(setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
((looking-at "\\<endinterface\\>")
;; 12: Search back for matching interface
(setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
@ -4751,6 +4825,16 @@ Set point to where line starts."
t)
((looking-at verilog-ovm-end-re)
t)
;; JBA find VMM macros
((looking-at verilog-vmm-statement-re)
nil )
((looking-at verilog-vmm-begin-re)
t)
((looking-at verilog-vmm-end-re)
nil)
;; JBA trying to catch macro lines with no ; at end
((looking-at "\\<`")
nil)
(t
(goto-char back)
(cond
@ -5475,7 +5559,7 @@ Be verbose about progress unless optional QUIET set."
(cond
((looking-at myre)
(goto-char (match-beginning 2))
(if (not (verilog-parenthesis-depth)) ;; ignore parenthsized exprs
(if (not (verilog-parenthesis-depth)) ;; ignore parenthesized exprs
(if (eq (char-after) ?=)
(indent-to (1+ ind)) ; line up the = of the <= with surrounding =
(indent-to ind)
@ -5607,7 +5691,7 @@ Region is defined by B and EDPOS."
(while (progn (setq e (marker-position edpos))
(< (point) e))
(if (and (verilog-re-search-forward myre e 'move)
(not (verilog-parenthesis-depth))) ;; skip parenthsized exprs
(not (verilog-parenthesis-depth))) ;; skip parenthesized exprs
(progn
(goto-char (match-beginning 2))
(verilog-backward-syntactic-ws)
@ -6645,8 +6729,14 @@ Return a array of [outputs inouts inputs wire reg assign const]."
((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
(goto-char (match-end 0))
(setq keywd (match-string 1))
(when (string-match "^\\\\" keywd)
(when (string-match "^\\\\" (match-string 1))
(setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
;; Add any :: package names to same identifier
(while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
(goto-char (match-end 0))
(setq keywd (concat keywd "::" (match-string 1)))
(when (string-match "^\\\\" (match-string 1))
(setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
(cond ((equal keywd "input")
(setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
expect-signal 'sigs-in io t modport nil))
@ -7917,7 +8007,7 @@ Cache the output of function so next call may have faster access."
(nth 3 fass))
(t
;; Read from file
;; Clear then restore any hilighting to make emacs19 happy
;; Clear then restore any highlighting to make emacs19 happy
(let ((fontlocked (when (and (boundp 'font-lock-mode)
font-lock-mode)
(font-lock-mode 0)
@ -8756,7 +8846,7 @@ If PAR-VALUES replace final strings with these parameter values."
"Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
;; Do we need a trailing comma?
;; There maybe a ifdef or something similar before us. What a mess. Thus
;; to avoid trouble we only insert on preceeding ) or *.
;; to avoid trouble we only insert on preceding ) or *.
;; Insert first port on new line
(insert "\n") ;; Must insert before search, so point will move forward if insert comma
(save-excursion
@ -10067,7 +10157,7 @@ registers set elsewhere in the always block.
Limitations:
AUTORESET will not clear memories.
AUTORESET uses <= if there are any <= assigmnents in the block,
AUTORESET uses <= if there are any <= assignments in the block,
else it uses =.
/*AUTORESET*/ presumes that any signals mentioned between the previous
@ -11143,7 +11233,7 @@ Files are checked based on `verilog-library-directories'."
(interactive)
(let ((reporter-prompt-for-summary-p t))
(reporter-submit-bug-report
"mac@verilog.com"
"mac@verilog.com, wsnyder@wsnyder.org"
(concat "verilog-mode v" verilog-mode-version)
'(
verilog-align-ifelse
@ -11185,23 +11275,22 @@ Files are checked based on `verilog-library-directories'."
nil nil
(concat "Hi Mac,
I want to report a bug. I've read the `Bugs' section of `Info' on
Emacs, so I know how to make a clear and unambiguous report. To get
to that Info section, I typed
M-x info RET m " invocation-name " RET m bugs RET
I want to report a bug.
Before I go further, I want to say that Verilog mode has changed my life.
I save so much time, my files are colored nicely, my co workers respect
my coding ability... until now. I'd really appreciate anything you
could do to help me out with this minor deficiency in the product.
If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.org.
You may also want to look at the Verilog-Mode FAQ, see
I've taken a look at the Verilog-Mode FAQ at
http://www.veripool.org/verilog-mode-faq.html.
To reproduce the bug, start a fresh Emacs via " invocation-name "
And, I've considered filing the bug on the issue tracker at
http://www.veripool.org/verilog-mode-bugs
since I realize that public bugs are easier for you to track,
and for others to search, but would prefer to email.
So, to reproduce the bug, start a fresh Emacs via " invocation-name "
-no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
the code included below.