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verilog-mode.el: Merge from upstream: prepare for lexical bindings.

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* verilog-mode.el (verilog-do-indent)
(verilog-indent-declaration, verilog-read-always-signals-recurse)
(verilog-read-decls): Prepare for lexical bindings.
This commit is contained in:
Wilson Snyder 2021-09-16 10:23:10 -04:00
parent a38675ca88
commit 85c7993631
1 changed files with 16 additions and 2 deletions
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18
lisp/progmodes/verilog-mode.el
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@ -9,7 +9,7 @@
;; Keywords: languages
;; The "Version" is the date followed by the decimal rendition of the Git
;; commit hex.
;; Version: 2021.09.01.191709444
;; Version: 2021.09.16.045775504
;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
;; file on 19/3/2008, and the maintainer agreed that when a bug is
@ -124,7 +124,7 @@
;;
;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "2021-09-01-b6d4104-vpo-GNU"
(defconst verilog-mode-version "2021-09-16-2ba7a90-vpo-GNU"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
@ -6805,6 +6805,8 @@ Only look at a few lines to determine indent level."
(verilog-do-indent (verilog-calculate-indent)))
(defun verilog-do-indent (indent-str)
;; `ind' is used in expressions stored in `verilog-indent-alist'.
(verilog--suppressed-warnings ((lexical ind)) (defvar ind))
(let ((type (car indent-str))
(ind (car (cdr indent-str))))
(cond
@ -7286,6 +7288,8 @@ If QUIET is non-nil, do not print messages showing the progress of line-up."
Line up the variable names based on previous declaration's indentation.
BASEIND is the base indent to offset everything."
(interactive)
;; `ind' is used in expressions stored in `verilog-indent-alist'.
(verilog--suppressed-warnings ((lexical ind)) (defvar ind))
(let ((pos (point-marker))
(lim (save-excursion
;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
@ -8639,6 +8643,13 @@ Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
(defun verilog-read-decls ()
"Compute signal declaration information for the current module at point.
Return an array of [outputs inouts inputs wire reg assign const gparam intf]."
(verilog--suppressed-warnings
((lexical sigs-intf sigs-var sigs-const sigs-assign sigs-var
sigs-gparam sigs-inout sigs-out sigs-in))
;; The local variable below are accessed via (symbol-value expect-signal).
(defvar sigs-intf) (defvar sigs-var) (defvar sigs-const)
(defvar sigs-assign) (defvar sigs-var) (defvar sigs-gparam)
(defvar sigs-inout) (defvar sigs-out) (defvar sigs-in))
(let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
(functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
in-modport in-clocking in-ign-to-semi ptype ign-prop
@ -9319,6 +9330,9 @@ Must call `verilog-read-auto-lisp-present' before this function."
EXIT-KEYWD is expression to stop at, nil if top level.
RVALUE is true if at right hand side of equal.
TEMP-NEXT is true to ignore next token, fake from inside case statement."
(verilog--suppressed-warnings ((lexical sigs-temp sigs-in sigs-out-unk))
;; The local variable below are accessed via (symbol-value got-list).
(defvar sigs-temp) (defvar sigs-in) (defvar sigs-out-unk))
(let* ((semi-rvalue (equal "endcase" exit-keywd)) ; true if after a ; we are looking for rvalue
keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
ignore-next)