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When verilog-auto-ignore-concat is true, also ignore parenthesized signals.

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* lisp/progmodes/verilog-mode.el (verilog-auto-ignore-concat): When
`verilog-auto-ignore-concat' is true, also ignore parenthesized
signals.
This commit is contained in:
Wilson Snyder 2019-11-21 14:38:09 -05:00
parent 03938ba381
commit 6c9c45bfab
1 changed files with 11 additions and 11 deletions
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22
lisp/progmodes/verilog-mode.el
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@ -9,7 +9,7 @@
;; Keywords: languages
;; The "Version" is the date followed by the decimal rendition of the Git
;; commit hex.
;; Version: 2019.11.11.038630457
;; Version: 2019.11.21.248091482
;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
;; file on 19/3/2008, and the maintainer agreed that when a bug is
@ -124,7 +124,7 @@
;;
;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "2019-11-11-24d7439-vpo-GNU"
(defconst verilog-mode-version "2019-11-21-ec9935a-vpo-GNU"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
@ -809,9 +809,7 @@ The name of the function or case will be set between the braces."
(defcustom verilog-auto-ignore-concat nil
"Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
This will exclude signals referenced as pin connections in {...}
from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
for backward compatibility only and not set in new designs; it
may be removed in future versions."
or (...) from AUTOWIRE, AUTOOUTPUT and friends."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
@ -8862,11 +8860,10 @@ Return an array of [outputs inouts inputs wire reg assign const]."
;; {..., a, b} requires us to recurse on a,b
;; To support {#{},{#{a,b}} we'll just split everything on [{},]
((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
(unless verilog-auto-ignore-concat
(let ((mlst (split-string (match-string 1 expr) "[{},]"))
mstr)
(while (setq mstr (pop mlst))
(verilog-read-sub-decls-expr submoddecls par-values comment port mstr)))))
(let ((mlst (split-string (match-string 1 expr) "[{},]"))
mstr)
(while (setq mstr (pop mlst))
(verilog-read-sub-decls-expr submoddecls par-values comment port mstr))))
(t
(let (sig vec multidim mem)
;; Remove leading reduction operators, etc
@ -8942,7 +8939,10 @@ Inserts the list of signals found, using submodi to look up each port."
;; We intentionally ignore (non-escaped) signals with .s in them
;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
(when port
(cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
(cond ((and verilog-auto-ignore-concat
(looking-at "[({]"))
nil) ; {...} or (...) historically ignored with auto-ignore-concat
((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
(verilog-read-sub-decls-sig
submoddecls par-values comment port
(verilog-string-remove-spaces (match-string-no-properties 1)) ; sig