* progmodes/verilog-mode.el (verilog-auto-inout-module):
Add optional regular expression to AUTOINOUTMODULE. (verilog-inject-auto, verilog-auto-arg, verilog-auto-inst) (verilog-auto-inst-param, verilog-auto-reg) (verilog-auto-reg-input, verilog-auto-wire, verilog-auto-output) (verilog-auto-output-every, verilog-auto-input) (verilog-auto-inout, verilog-auto-sense, verilog-auto-tieoff) (verilog-auto-unused, verilog-auto): Update documentation to use more obvious instance module names versus cell names.
This commit is contained in:
Dan Nicolaescu
parent
0d22595df5
commit
1dd4b00465
2 changed files with 168 additions and 117 deletions
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@ -1,3 +1,15 @@
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2008-03-28 Wilson Snyder <wsnyder@wsnyder.org>
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* progmodes/verilog-mode.el (verilog-auto-inout-module):
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Add optional regular expression to AUTOINOUTMODULE.
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(verilog-inject-auto, verilog-auto-arg, verilog-auto-inst)
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(verilog-auto-inst-param, verilog-auto-reg)
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(verilog-auto-reg-input, verilog-auto-wire, verilog-auto-output)
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(verilog-auto-output-every, verilog-auto-input)
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(verilog-auto-inout, verilog-auto-sense, verilog-auto-tieoff)
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(verilog-auto-unused, verilog-auto): Update documentation to use
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more obvious instance module names versus cell names.
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2008-03-28 Jan Djärv <jan.h.d@swipnet.se>
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* progmodes/compile.el (compilation-mode-tool-bar-map): Only enable
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@ -6354,7 +6354,7 @@ component library to determine connectivity of the design.
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One work around for this problem is to manually create // Inputs and //
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Outputs comments above subcell signals, for example:
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module1 instance1x (
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module ModuleName (
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// Outputs
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.out (out),
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// Inputs
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@ -7705,29 +7705,31 @@ support adding new ports. You may wish to delete older ports yourself.
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For example:
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module ex_inject (i, o);
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module ExampInject (i, o);
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input i;
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input j;
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output o;
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always @ (i or j)
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o = i | j;
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cell cell (.foobar(baz),
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.j(j));
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InstModule instName
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(.foobar(baz),
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j(j));
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endmodule
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Typing \\[verilog-inject-auto] will make this into:
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module ex_inject (i, o/*AUTOARG*/
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module ExampInject (i, o/*AUTOARG*/
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// Inputs
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j);
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input i;
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output o;
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always @ (/*AS*/i or j)
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o = i | j;
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cell cell (.foobar(baz),
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/*AUTOINST*/
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// Outputs
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.j(j));
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InstModule instName
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(.foobar(baz),
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/*AUTOINST*/
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// Outputs
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j(j));
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endmodule"
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(interactive)
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(verilog-auto t))
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@ -7893,14 +7895,14 @@ Limitations:
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For example:
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module ex_arg (/*AUTOARG*/);
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module ExampArg (/*AUTOARG*/);
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input i;
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output o;
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endmodule
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Typing \\[verilog-auto] will make this into:
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module ex_arg (/*AUTOARG*/
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module ExampArg (/*AUTOARG*/
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// Outputs
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o,
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// Inputs
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@ -8082,9 +8084,9 @@ Limitations:
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SystemVerilog multidimensional input/output has only experimental support.
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For example, first take the submodule inst.v:
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For example, first take the submodule InstModule.v:
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module inst (o,i)
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module InstModule (o,i)
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output [31:0] o;
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input i;
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wire [31:0] o = {32{i}};
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@ -8092,22 +8094,24 @@ For example, first take the submodule inst.v:
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This is then used in a upper level module:
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module ex_inst (o,i)
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module ExampInst (o,i)
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output o;
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input i;
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inst inst (/*AUTOINST*/);
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InstModule instName
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(/*AUTOINST*/);
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endmodule
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Typing \\[verilog-auto] will make this into:
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module ex_inst (o,i)
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module ExampInst (o,i)
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output o;
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input i;
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inst inst (/*AUTOINST*/
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// Outputs
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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InstModule instName
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(/*AUTOINST*/
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// Outputs
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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endmodule
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Where the list of inputs and outputs came from the inst module.
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@ -8129,11 +8133,12 @@ Exceptions:
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you have the appropriate // Input or // Output comment, and exactly the
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same line formatting as AUTOINST itself uses.
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inst inst (// Inputs
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.i (my_i_dont_mess_with_it),
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/*AUTOINST*/
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// Outputs
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.ov (ov[31:0]));
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InstModule instName
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(// Inputs
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.i (my_i_dont_mess_with_it),
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/*AUTOINST*/
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// Outputs
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.ov (ov[31:0]));
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Templates:
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@ -8141,7 +8146,7 @@ Templates:
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For multiple instantiations based upon a single template, create a
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commented out template:
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/* instantiating_module_name AUTO_TEMPLATE (
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/* InstModule AUTO_TEMPLATE (
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.sig3 (sigz[]),
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);
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*/
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@ -8170,15 +8175,15 @@ Templates:
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For example:
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/* psm_mas AUTO_TEMPLATE (
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/* InstModule AUTO_TEMPLATE (
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.ptl_bus (ptl_busnew[]),
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);
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*/
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psm_mas ms2m (/*AUTOINST*/);
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InstModule ms2m (/*AUTOINST*/);
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Typing \\[verilog-auto] will make this into:
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psm_mas ms2m (/*AUTOINST*/
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InstModule ms2m (/*AUTOINST*/
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// Outputs
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.NotInTemplate (NotInTemplate),
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.ptl_bus (ptl_busnew[3:0]), // Templated
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@ -8189,7 +8194,7 @@ Templates:
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It is common to instantiate a cell multiple times, so templates make it
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trivial to substitute part of the cell name into the connection name.
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/* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> (
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/* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
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.sig1 (sigx[@]),
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.sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
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);
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@ -8211,16 +8216,16 @@ Templates:
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For example:
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/* psm_mas AUTO_TEMPLATE (
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/* InstModule AUTO_TEMPLATE (
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.ptl_mapvalidx (ptl_mapvalid[@]),
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.ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
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);
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*/
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psm_mas ms2m (/*AUTOINST*/);
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InstModule ms2m (/*AUTOINST*/);
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Typing \\[verilog-auto] will make this into:
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psm_mas ms2m (/*AUTOINST*/
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InstModule ms2m (/*AUTOINST*/
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// Outputs
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.ptl_mapvalidx (ptl_mapvalid[2]),
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.ptl_mapvalidp1x (ptl_mapvalid[3]));
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@ -8229,21 +8234,21 @@ Templates:
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Alternatively, using a regular expression for @:
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/* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
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/* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
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.ptl_mapvalidx (@_ptl_mapvalid),
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.ptl_mapvalidp1x (ptl_mapvalid_@),
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);
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*/
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psm_mas ms2_FOO (/*AUTOINST*/);
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psm_mas ms2_BAR (/*AUTOINST*/);
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InstModule ms2_FOO (/*AUTOINST*/);
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InstModule ms2_BAR (/*AUTOINST*/);
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Typing \\[verilog-auto] will make this into:
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psm_mas ms2_FOO (/*AUTOINST*/
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InstModule ms2_FOO (/*AUTOINST*/
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// Outputs
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.ptl_mapvalidx (FOO_ptl_mapvalid),
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.ptl_mapvalidp1x (ptl_mapvalid_FOO));
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psm_mas ms2_BAR (/*AUTOINST*/
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InstModule ms2_BAR (/*AUTOINST*/
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// Outputs
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.ptl_mapvalidx (BAR_ptl_mapvalid),
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.ptl_mapvalidp1x (ptl_mapvalid_BAR));
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@ -8289,8 +8294,8 @@ Lisp Templates:
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vl-width Width of the input/output port ('3' for [2:0]).
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May be a (...) expression if bits isn't a constant.
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vl-dir Direction of the pin input/output/inout.
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vl-cell-type Module name/type of the cell ('psm_mas').
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vl-cell-name Instance name of the cell ('ms2m').
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vl-cell-type Module name/type of the cell ('InstModule').
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vl-cell-name Instance name of the cell ('instName').
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Normal Lisp variables may be used in expressions. See
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`verilog-read-defines' which can set vh-{definename} variables for use
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@ -8400,29 +8405,29 @@ automatically derived from the module header of the instantiated netlist.
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See \\[verilog-auto-inst] for limitations, and templates to customize the
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output.
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For example, first take the submodule inst.v:
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For example, first take the submodule InstModule.v:
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module inst (o,i)
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module InstModule (o,i)
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parameter PAR;
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endmodule
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This is then used in a upper level module:
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module ex_inst (o,i)
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module ExampInst (o,i)
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parameter PAR;
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inst #(/*AUTOINSTPARAM*/)
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inst (/*AUTOINST*/);
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InstModule #(/*AUTOINSTPARAM*/)
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instName (/*AUTOINST*/);
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endmodule
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Typing \\[verilog-auto] will make this into:
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module ex_inst (o,i)
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module ExampInst (o,i)
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output o;
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input i;
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inst (/*AUTOINSTPARAM*/
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// Parameters
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.PAR (PAR));
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inst (/*AUTOINST*/);
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InstModule #(/*AUTOINSTPARAM*/
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// Parameters
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.PAR (PAR));
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instName (/*AUTOINST*/);
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endmodule
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Where the list of parameter connections come from the inst module.
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@ -8506,7 +8511,7 @@ Limitations:
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An example:
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module ex_reg (o,i)
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module ExampReg (o,i)
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output o;
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input i;
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/*AUTOREG*/
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@ -8515,12 +8520,12 @@ An example:
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Typing \\[verilog-auto] will make this into:
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module ex_reg (o,i)
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module ExampReg (o,i)
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output o;
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input i;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg o;
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reg o;
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// End of automatics
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always o = i;
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endmodule"
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@ -8557,27 +8562,29 @@ Limitations:
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An example (see `verilog-auto-inst' for what else is going on here):
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module ex_reg_input (o,i)
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module ExampRegInput (o,i)
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output o;
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input i;
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/*AUTOREGINPUT*/
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inst inst (/*AUTOINST*/);
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InstModule instName
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(/*AUTOINST*/);
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endmodule
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Typing \\[verilog-auto] will make this into:
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module ex_reg_input (o,i)
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module ExampRegInput (o,i)
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output o;
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input i;
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/*AUTOREGINPUT*/
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// Beginning of automatic reg inputs (for undeclared ...
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reg [31:0] iv; // From inst of inst.v
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reg [31:0] iv; // From inst of inst.v
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// End of automatics
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inst inst (/*AUTOINST*/
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// Outputs
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.o (o[31:0]),
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// Inputs
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.iv (iv));
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InstModule instName
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(/*AUTOINST*/
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// Outputs
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.o (o[31:0]),
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// Inputs
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.iv (iv));
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endmodule"
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(save-excursion
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;; Point must be at insertion point.
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@ -8615,27 +8622,29 @@ Limitations:
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An example (see `verilog-auto-inst' for what else is going on here):
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module ex_wire (o,i)
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module ExampWire (o,i)
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output o;
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input i;
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/*AUTOWIRE*/
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inst inst (/*AUTOINST*/);
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InstModule instName
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(/*AUTOINST*/);
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endmodule
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Typing \\[verilog-auto] will make this into:
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module ex_wire (o,i)
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module ExampWire (o,i)
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output o;
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input i;
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/*AUTOWIRE*/
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// Beginning of automatic wires
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wire [31:0] ov; // From inst of inst.v
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// End of automatics
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inst inst (/*AUTOINST*/
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// Outputs
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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InstModule instName
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(/*AUTOINST*/
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// Outputs
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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wire o = | ov;
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endmodule"
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(save-excursion
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@ -8681,25 +8690,27 @@ Limitations:
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|
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An example (see `verilog-auto-inst' for what else is going on here):
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module ex_output (ov,i)
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module ExampOutput (ov,i)
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input i;
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/*AUTOOUTPUT*/
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inst inst (/*AUTOINST*/);
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InstModule instName
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(/*AUTOINST*/);
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endmodule
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Typing \\[verilog-auto] will make this into:
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module ex_output (ov,i)
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module ExampOutput (ov,i)
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input i;
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
|
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output [31:0] ov; // From inst of inst.v
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output [31:0] ov; // From inst of inst.v
|
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// End of automatics
|
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inst inst (/*AUTOINST*/
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// Outputs
|
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.ov (ov[31:0]),
|
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// Inputs
|
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.i (i));
|
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InstModule instName
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(/*AUTOINST*/
|
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// Outputs
|
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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endmodule
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You may also provide an optional regular expression, in which case only
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|
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@ -8743,7 +8754,7 @@ won't optimize away the outputs.
|
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|
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An example:
|
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|
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module ex_output_every (o,i,tempa,tempb)
|
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module ExampOutputEvery (o,i,tempa,tempb)
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output o;
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input i;
|
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/*AUTOOUTPUTEVERY*/
|
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|
|
@ -8754,13 +8765,13 @@ An example:
|
|||
|
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Typing \\[verilog-auto] will make this into:
|
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|
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module ex_output_every (o,i,tempa,tempb)
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module ExampOutputEvery (o,i,tempa,tempb)
|
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output o;
|
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input i;
|
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/*AUTOOUTPUTEVERY*/
|
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// Beginning of automatic outputs (every signal)
|
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output tempb;
|
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output tempa;
|
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output tempb;
|
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output tempa;
|
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// End of automatics
|
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wire tempa = i;
|
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wire tempb = tempa;
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|
|
@ -8805,25 +8816,27 @@ Limitations:
|
|||
|
||||
An example (see `verilog-auto-inst' for what else is going on here):
|
||||
|
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module ex_input (ov,i)
|
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module ExampInput (ov,i)
|
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output [31:0] ov;
|
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/*AUTOINPUT*/
|
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inst inst (/*AUTOINST*/);
|
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InstModule instName
|
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(/*AUTOINST*/);
|
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endmodule
|
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|
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Typing \\[verilog-auto] will make this into:
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|
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module ex_input (ov,i)
|
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module ExampInput (ov,i)
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output [31:0] ov;
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/*AUTOINPUT*/
|
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// Beginning of automatic inputs (from unused autoinst inputs)
|
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input i; // From inst of inst.v
|
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input i; // From inst of inst.v
|
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// End of automatics
|
||||
inst inst (/*AUTOINST*/
|
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// Outputs
|
||||
.ov (ov[31:0]),
|
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// Inputs
|
||||
.i (i));
|
||||
InstModule instName
|
||||
(/*AUTOINST*/
|
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// Outputs
|
||||
.ov (ov[31:0]),
|
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// Inputs
|
||||
.i (i));
|
||||
endmodule
|
||||
|
||||
You may also provide an optional regular expression, in which case only
|
||||
|
|
@ -8881,25 +8894,27 @@ Limitations:
|
|||
|
||||
An example (see `verilog-auto-inst' for what else is going on here):
|
||||
|
||||
module ex_inout (ov,i)
|
||||
module ExampInout (ov,i)
|
||||
input i;
|
||||
/*AUTOINOUT*/
|
||||
inst inst (/*AUTOINST*/);
|
||||
InstModule instName
|
||||
(/*AUTOINST*/);
|
||||
endmodule
|
||||
|
||||
Typing \\[verilog-auto] will make this into:
|
||||
|
||||
module ex_inout (ov,i)
|
||||
module ExampInout (ov,i)
|
||||
input i;
|
||||
/*AUTOINOUT*/
|
||||
// Beginning of automatic inouts (from unused autoinst inouts)
|
||||
inout [31:0] ov; // From inst of inst.v
|
||||
inout [31:0] ov; // From inst of inst.v
|
||||
// End of automatics
|
||||
inst inst (/*AUTOINST*/
|
||||
// Inouts
|
||||
.ov (ov[31:0]),
|
||||
// Inputs
|
||||
.i (i));
|
||||
InstModule instName
|
||||
(/*AUTOINST*/
|
||||
// Inouts
|
||||
.ov (ov[31:0]),
|
||||
// Inputs
|
||||
.i (i));
|
||||
endmodule
|
||||
|
||||
You may also provide an optional regular expression, in which case only
|
||||
|
|
@ -8956,11 +8971,11 @@ Limitations:
|
|||
|
||||
An example:
|
||||
|
||||
module ex_shell (/*AUTOARG*/)
|
||||
/*AUTOINOUTMODULE(\"ex_main\")*/
|
||||
module ExampShell (/*AUTOARG*/)
|
||||
/*AUTOINOUTMODULE(\"ExampMain\")*/
|
||||
endmodule
|
||||
|
||||
module ex_main (i,o,io)
|
||||
module ExampMain (i,o,io)
|
||||
input i;
|
||||
output o;
|
||||
inout io;
|
||||
|
|
@ -8968,16 +8983,25 @@ An example:
|
|||
|
||||
Typing \\[verilog-auto] will make this into:
|
||||
|
||||
module ex_shell (/*AUTOARG*/i,o,io)
|
||||
/*AUTOINOUTMODULE(\"ex_main\")*/
|
||||
module ExampShell (/*AUTOARG*/i,o,io)
|
||||
/*AUTOINOUTMODULE(\"ExampMain\")*/
|
||||
// Beginning of automatic in/out/inouts (from specific module)
|
||||
input i;
|
||||
output o;
|
||||
inout io;
|
||||
// End of automatics
|
||||
endmodule"
|
||||
endmodule
|
||||
|
||||
You may also provide an optional regular expression, in which case only
|
||||
signals matching the regular expression will be included. For example the
|
||||
same expansion will result from only extracting signals starting with i:
|
||||
|
||||
/*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/"
|
||||
(save-excursion
|
||||
(let* ((submod (car (verilog-read-auto-params 1))) submodi)
|
||||
(let* ((params (verilog-read-auto-params 1 2))
|
||||
(submod (nth 0 params))
|
||||
(regexp (nth 1 params))
|
||||
submodi)
|
||||
;; Lookup position, etc of co-module
|
||||
;; Note this may raise an error
|
||||
(when (setq submodi (verilog-modi-lookup submod t))
|
||||
|
|
@ -8994,6 +9018,13 @@ Typing \\[verilog-auto] will make this into:
|
|||
(verilog-modi-get-inouts submodi)
|
||||
(append (verilog-modi-get-inouts modi)))))
|
||||
(forward-line 1)
|
||||
(when regexp
|
||||
(setq sig-list-i (verilog-signals-matching-regexp
|
||||
sig-list-i regexp)
|
||||
sig-list-o (verilog-signals-matching-regexp
|
||||
sig-list-o regexp)
|
||||
sig-list-io (verilog-signals-matching-regexp
|
||||
sig-list-io regexp)))
|
||||
(when v2k (verilog-repair-open-comma))
|
||||
(when (or sig-list-i sig-list-o sig-list-io)
|
||||
(verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
|
||||
|
|
@ -9052,7 +9083,7 @@ OOps!
|
|||
|
||||
An example:
|
||||
|
||||
always @ (/*AUTOSENSE*/) begin
|
||||
always @ (/*AS*/) begin
|
||||
/* AUTO_CONSTANT (`constant) */
|
||||
outin = ina | inb | `constant;
|
||||
out = outin;
|
||||
|
|
@ -9060,10 +9091,18 @@ An example:
|
|||
|
||||
Typing \\[verilog-auto] will make this into:
|
||||
|
||||
always @ (/*AUTOSENSE*/ina or inb) begin
|
||||
always @ (/*AS*/ina or inb) begin
|
||||
/* AUTO_CONSTANT (`constant) */
|
||||
outin = ina | inb | `constant;
|
||||
out = outin;
|
||||
end
|
||||
|
||||
Note in Verilog 2001, you can often get the same result from the new @*
|
||||
operator. (This was added to the language in part due to AUTOSENSE!)
|
||||
|
||||
always @* begin
|
||||
outin = ina | inb | `constant;
|
||||
out = outin;
|
||||
end"
|
||||
(save-excursion
|
||||
;; Find beginning
|
||||
|
|
@ -9219,7 +9258,7 @@ them to a one.
|
|||
|
||||
An example of making a stub for another module:
|
||||
|
||||
module FooStub (/*AUTOINST*/);
|
||||
module ExampStub (/*AUTOINST*/);
|
||||
/*AUTOINOUTMODULE(\"Foo\")*/
|
||||
/*AUTOTIEOFF*/
|
||||
// verilator lint_off UNUSED
|
||||
|
|
@ -9231,7 +9270,7 @@ An example of making a stub for another module:
|
|||
|
||||
Typing \\[verilog-auto] will make this into:
|
||||
|
||||
module FooStub (/*AUTOINST*/...);
|
||||
module ExampStub (/*AUTOINST*/...);
|
||||
/*AUTOINOUTMODULE(\"Foo\")*/
|
||||
// Beginning of autotieoff
|
||||
output [2:0] foo;
|
||||
|
|
@ -9300,8 +9339,8 @@ You can add signals you do not want included in AUTOUNUSED with
|
|||
|
||||
An example of making a stub for another module:
|
||||
|
||||
module FooStub (/*AUTOINST*/);
|
||||
/*AUTOINOUTMODULE(\"Foo\")*/
|
||||
module ExampStub (/*AUTOINST*/);
|
||||
/*AUTOINOUTMODULE(\"Examp\")*/
|
||||
/*AUTOTIEOFF*/
|
||||
// verilator lint_off UNUSED
|
||||
wire _unused_ok = &{1'b0,
|
||||
|
|
@ -9524,12 +9563,12 @@ The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
|
|||
called before and after this function, respectively.
|
||||
|
||||
For example:
|
||||
module (/*AUTOARG*/)
|
||||
module ModuleName (/*AUTOARG*/)
|
||||
/*AUTOINPUT*/
|
||||
/*AUTOOUTPUT*/
|
||||
/*AUTOWIRE*/
|
||||
/*AUTOREG*/
|
||||
somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
|
||||
InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
|
||||
|
||||
You can also update the AUTOs from the shell using:
|
||||
emacs --batch <filenames.v> -f verilog-batch-auto
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue